【Member News】NCT Gallium Oxide Transistors Set New Record for Device Performance in the World - With the Latest Guard Ring Structure, the Performance of the Previous Power Device is Improved by 3.2 Times -

      Novel Crystal Technology, Inc. (Headquarters: Kazayama City, Saitama Prefecture, President Akito Kuramata) in the Security Technology Research and Promotion Program under the Acquisition, Technology & Logistics Agency (ATLA) (JP004596) "Research and Development of Reverse MOS Channel Type Gallium Oxide Transistor" project, A Gallium Oxide vertical MOS transistor (β-Ga₂O₃ MOSFET) with a Power Figure of Merit (PFOM) of 1.23 GW/cm² has been successfully developed. This PFOM is the highest in the world in the field of β-Ga₂O₃ FETs, and 3.2 times the highest value of β- Ga₂O₃ FETs published by other research institutions.

      This research has made significant progress in the development of mid to high withstand voltage (0.6-10 kV) Gallium Oxide transistors, which will promote the low cost and high performance of power electronics technology. In addition, by improving the efficiency and miniaturization of power electronic equipment such as industrial inverters and power supplies, it is expected to promote the further development of efficient power conversion devices for electric vehicles, flying cars and other electric energy, as well as solar, wind and other renewable energy generation and power system. Details of the results will be presented on March 15, 2025, at the 72nd Society for Applied Physics Spring Lecture, under the title "Verification of Power FOM 1.23 GW/cm²  via β-Ga₂O₃ FinFET."

 

Overview

      As a high-performance alternative to Silicon, Gallium Oxide (β-Ga₂O₃) ^※1, compared with Silicon Carbide (SiC) ^※2 and Gallium Nitride (GaN) ^※3, which are also under development, can produce low-loss and low-cost power devices^※4 by virtue of its excellent material properties and low-cost crystal growth methods. Therefore, the application of β-Ga₂O₃ in various power electronic devices such as home appliances, industrial equipment, electric vehicles, railway vehicles, solar power generation, wind power generation is highly anticipated. In addition, due to its ability to achieve miniaturization and high efficiency of carrying electrical equipment, domestic and foreign enterprises and research institutions are also accelerating related research and development.

      Novel Crystal Technology, Inc. has been working since 2019 to realize the productization goal of β-Ga₂O₃ MOSFET. Participated in the projects of "Research and Development of 10 kV Class Gallium Oxide Channel MOSFET" and "Research and Development of Reverse MOS Channel Type Gallium Oxide Transistor" under the Security Technology Research and Promotion Program under the Acquisition, Technology & Logistics Agency (ATLA). This time, the world's highest Power Figure of Merit (PFOM)^※6 of the β-Ga₂O₃  MOSFET was successfully achieved by setting a high-resistance guard ring structure^※5 formed by Mg ion implantation at the gate electrode termination of the MOSFET with a high withstand voltage β-Ga₂O₃  drift layer. This development will promote the development of mid and high withstand voltage (0.6-10 kV) Gallium Oxide transistors, which will bring significant progress in low-cost and high-performance power electronics technology.

 

Research Result

      Previously, NCT's research and development of β-Ga₂O₃ MOSFET failed to give full play to its advantages of high insulation breakdown electric field strength (6~8 MV/cm) due to the issue of electric field concentration at the gate electrode termination. Traditional power semiconductors (such as SiC, GaN) usually use P-type conductive layers^※7 to mitigate electric field concentration, but Gallium Oxide has not established a mature P-type conductive layer technology, so it is impossible to apply the same method to Gallium Oxide.

      To overcome this problem, we use Mg ion implantation^※9 to form deep level accepter impurity^※8 in Gallium Oxide, and construct high resistance guard ring structure by activation heat treatment^※10.

FIG. 1. Brief diagram of β-Ga₂O₃ MOSFET

      Figure 1 shows the cross-sectional structure and plane layout of the β-Ga₂O₃ MOSFET developed in this project. The transistor has the following characteristics:

      · Adopting a vertical device structure that is conducive to low loss and high current.

      · With Multi-Fin structure^※11, it can realize Normally-Off characteristic without P-type conductive layer;

      · High withstand voltage Ga₂O₃ drift layer with donor concentration of 7.5 × 10¹⁵ cm^-3 and thickness of 55 µm;

      · Mg ion implantation guard ring was introduced in the β-Ga₂O₃ region at the electrode termination to effectively mitigate the electric field concentration issue.

      The β-Ga₂O₃ MOSFET are designed with a mesa width of 0.2 µm, a gate length of 3.5 µm, a Fin length of 70 µm, and a fin spacing of 5 µm, consisting of 10 fins.

FIG. 2. Drain current-voltage characteristics

      Figure 2 shows the drain current-voltage characteristics of a test β-Ga₂O₃ MOSFET. The maximum current density normalized by source area (50 µm × 60 µm) is 218 A/cm² and the specific on-resistance is 21.6 mΩ·cm² (V_gs = 5 V).

FIG. 3. Drain current · Gate current - Gate voltage characteristics

      Figure 3 shows the drain current and the gate current in relation to the gate voltage. The drain current on/off ratio is improved by more than 8 orders of magnitude, with a sub-threshold swing^※12 of 162 mV/decade, showing excellent transistor characteristics.

FIG. 4. Transistor withstand voltage waveform

      Figure 4 shows the source and gate current characteristics when a positive voltage is applied to the drain while the gate and source voltages are fixed at 0 V. The breakdown voltage was increased to 5.15 kV from the previous 1.6 kV by using a guard ring structure with Mg ion implantation. Before and after the introduction of the guard ring structure, the maximum electric field strength in the β-Ga₂O₃ drift layer is estimated to be 2 MV/cm and 3.72 MV/cm respectively. The researchers believe that the Mg-implanted guard ring mitigates the electric field concentration at the gate edge, allowing the electric field strength in the drift layer to be increased.

FIG. 5. Characteristic on-resistance and breakdown voltage of MOSFET

      Figure 5 shows the relationship between the characteristic on-resistance (R_on,sp) and the breakdown voltage (V_br), which is a performance indicator of a power device. The breakdown voltage is significantly improved by guard ring structure formed by implanting Mg ions into β-Ga₂O₃ in the electrode termination zone. As a result, a good PFOM value of 1.23 GW/cm² was obtained, 13.3 times higher than before the guard ring was used. The PFOM value is now the highest among β-Ga₂O₃ FETs worldwide and 3.2 times higher than the highest β- Ga₂O₃ FETs published by other research institutions.

 

Future Outlook

      In the future, the researchers will further optimize the terminal structure of the β-Ga₂O₃ MOSFET, including the introduction of heterogeneous P-type semiconductor materials such as NiO, to further alleviate the problem of electric field concentration at the electrode termination. Through this technology, it is hoped that the high breakdown electric field strength (6~8 MV/cm) of β-Ga₂O₃ can be fully utilized to achieve high-performance Gallium Oxide power transistors beyond SiC.

 

Terminology Explanation

※1 Gallium Oxide (β-Ga₂O₃) : Gallium Oxide, a compound of gallium and oxygen, is a wide band gap semiconductor material.

※2 Silicon Carbide (SiC): A compound of silicon and carbon, a wide band gap semiconductor material

※3 Gallium Nitride (GaN) : A compound of gallium and nitrogen, a wide band gap semiconductor material.

※4 Power devices: Semiconductor components that can control high voltage and high current, such as inverters.

※5 Guard ring structure: A structure designed to mitigate electric field concentration by placing a conductive layer of a different type than the drift layer in the region where the electric field tends to concentrate at the electrode termination. This structure laterally extends the equipotential surfaces, thereby alleviating electric field concentration.

※6 Power Figure of Merit (PFOM) : The formula is V_br²/R_on,sp; An important indicator used to evaluate the performance of power devices. The larger the value, the better the performance.

※7 P-type conductive layer: A semiconductor layer in which the current carrying particles in a conductive semiconductor are holes rather than electrons.

※8 Acceptor impurities: Acceptor impurities are impurities in semiconductors that trap electrons and are negatively charged. Normally, the acceptor impurity creates holes in the semiconductor by trapping electrons, thus making the semiconductor a P-type semiconductor.

※9 Ion implantation: Ion implantation is a technique for adding impurities to a semiconductor. The principle is to ionize the impurity atoms and accelerate the injection into the semiconductor material through a high voltage of tens of kilovolts (kV) to hundreds of kilovolts.

※10 Activation heat treatment: The process of repairing the damage caused by the semiconductor material during ion implantation by high temperature treatment and promoting the electrical activity of the implanted impurities. Temperatures usually used range from 600°C to 1200°C.

※11 Fin-type structure (FinFET) : Fin-type structure refers to a channel section design in which the gate is located on either side of the channel or wrapped around the channel to form a double-gate or multi-gate structure. It is called a "finfET" because its shape resembles that of a fish fin.

※12 Subthreshold swing: The subthreshold swing is a measure of the transistor's turn-off performance and represents the amount of change in gate voltage required to increase the drain current by an order of magnitude. The subthreshold swing will increase (i.e., performance degradation) due to a decline in the quality of the MOS interface.