【Domestic Papers】High-performance Sn-doped Ga₂O₃ FETs by co-sputtering: Depletion mode versus enhancement mode

      Researchers from the Beijing Institute of Technology have published a dissertation titled "High-performance Sn-doped Ga₂O₃ FETs by co-sputtering: Depletion mode versus enhancement mode" in Materials Science in Semiconductor Processing.

Project Support

      This work was supported by the National Key R&D Program of China(No.2023YFB3611700) and National Natural Science Foundation of China(92163206, 12321004).

Background

      As an ultrawide-bandgap semiconductor, gallium oxide (Ga₂O₃) typically presents a bandgap larger than 4.5 eV and a high critical breakdown field of 8 MV/cm. Besides, the Baliga figure of merit (BFOM) of Ga₂O₃ can theoretically exceed 3000, which is significantly larger than those of GaN (∼870) and SiC (∼340). Recently, Ga₂O₃ has been extensively explored for field-effect transistors (FETs), the current capability of which can be effectively improved with Sn, Ge, and Si doping. Specifically, Sn dopants in Ga₂O₃, existing as Sn⁴⁺ to substitute Ga³⁺, elevate electron concentration, enabling a conversion from insulator-like pristine Ga₂O₃ to semiconductor. This conversion can notably boost the on-state current (I_ON) of the Ga₂O₃ FETs more than 10⁷ times. However, FETs with doped Ga₂O₃ are always in depletion-mode (d-mode) operation but the enhancement-mode (e-mode) devices are desirable because the normally-off operation is safe and energy-saving for power applications. One method to fabricate e-mode doped-Ga₂O₃ FETs is to intentionally reduce the channel carrier density, which can simultaneously decrease the I_ON. Another method is to adopt novel device architectures like fin-shaped channels and vertical transistors, which can complicate fabrication processes and raise production costs. Moreover, high temperature and homogeneous substrates are always required in the preparation of Ga₂O₃, limiting the handy modulation of operation modes and mass production feasibility.

Abstract

      High-performance Sn-doped gallium oxide (Ga₂O₃) films were deposited on Si/SiO₂ substrates to fabricate field-effect transistors (FETs) via room-temperature co-sputtering. The performances of the SiO₂-supported FETs were optimized by varying the co-sputtering power of Sn to demonstrate a large on-state current (I_ON) of 2.5 mA/mm and a high on/off ratio of over 10⁶. However, it is accompanied by a normally-on behavior with a negative threshold voltage (V_TH), namely depletion mode (d-mode). Importantly, this d-mode can be converted to enhancement mode (e-mode) by adopting high-k Ta₂O₅/pristine Ga₂O₃ dielectrics, and extra nitrogen (N) doping in the Sn-doped Ga₂O₃ channels. Finally, the performances of the e-mode FETs with high-k dielectrics can be promoted via a Sn-doped Ga₂O₃/(Sn, N)-doped Ga₂O₃ dual-layer channel structure, which presents a large I_ON over 2 mA/mm, a high on/off ratio exceeding 10⁷, and a small V_TH below 5 V. Furthermore, the FET with dual-layer channel shows excellent stability, which is reflected by the bias stress measurement and stable performances after 3-month exposure to air. This remarkably-improved performance is attributed to the enhanced field effect by the high-k dielectrics, and the dual-layer channel structure that possesses both high stability of the (Sn, N)-doped layer and high current capability of the Sn-doped layer.

Highlights

      • High-performance Sn-doped Ga₂O₃FETs are fabricated via co-sputtering method.

      • The conversion from depletion mode to enhancement mode is successfully achieved.

      • Excellent stability is obtained by developing a dual-layer channel of (Sn, N)-doped Ga₂O₃/Sn-doped Ga₂O₃.

Conclusions

      In this work, e-mode Sn-doped Ga₂O₃ FETs with high-k Ta₂O₅ gate dielectrics were fabricated by co-sputtering at room temperature. Based on the high-k Ta₂O₅, other methods of pristine Ga₂O₃ buffer layer for Ta₂O₅, nitrogen doping, and dual-layer channel are further explored, which significantly reduce the I_OFF and positively shift the V_TH to achieve the e-mode operation. Moreover, the device with dual-layer channel exhibits excellent stability for long-term storage and bias-stress measurement. Finally, averaged over 20 devices, the dual-channel FETs with high-k Ta₂O₅/pristine Ga₂O₃ dielectrics show a high I_ON over 2 mA/mm, a large I_ON/I_OFF over 2 × 10⁷, and a small positive V_TH below 5 V. Therefore, this study provides an efficient and low-cost method for the wafer-scale fabrication of Si-compatible Ga₂O₃ nanodevices to enable low-temperature processing and facilitates heterogeneous power integration. Moreover, the high performances in this work can also highlight the versatility and potential of these devices for a wide range of electronic devices.