【Patenes】Gallium Oxide Patent Weekly Report (Issue 5, July)

Introduction

      To further strengthen information exchange within the gallium oxide industry and help stakeholders stay informed of the latest technological developments, the Asian Gallium Oxide Alliance (AGOA) has launched the Gallium Oxide Patent Weekly column. This series will continuously compile and publish newly disclosed patent applications and technological advances in the gallium oxide field.

      As an important indicator of technological innovation, patents reflect R&D trends and strategic layout across the industrial chain. This column focuses on crystal growth, material preparation, defect engineering, device development, process optimization, and emerging applications, providing enterprises, universities, and research institutes with insights into technology trends while supporting the continued development of the gallium oxide industry.

      This fifth issue reviews gallium oxide-related patent applications published during the fifth week of July 2026 (July 27 – August 2).

01 A Semiconductor Device and Manufacturing Method Thereof (Published on July 28)

      According to information released by the China National Intellectual Property Administration (CNIPA), Wuxi CR Microelectronics Co., Ltd. has filed a patent application titled “A Semiconductor Device and Manufacturing Method Thereof”, with publication number CN122476653A and application number 2026106678177.

      The patent discloses a semiconductor device and its fabrication method, including a doped gallium oxide epitaxial layer located on a substrate and a gallium oxide channel layer positioned on the doped epitaxial layer. The gallium oxide channel layer comprises at least one stacked structure, with each stacked structure consisting of a first doped gallium oxide layer and a gallium oxide layer with a gradient doping concentration.

      By constructing a composite gallium oxide channel layer composed of multiple stacked structures, the proposed technology aims to overcome the conventional carrier concentration limitations associated with doping. It enables an ultra-high carrier concentration for achieving an ultra-low-resistance channel layer, while simultaneously improving carrier mobility. This approach provides a critical material foundation and technical pathway for the development of high-performance and highly reliable gallium oxide power devices.

02 An Interface Engineering Method for Gallium Oxide-Based Semiconductor Devices and Semiconductor Structures and Ga₂O₃ MOSFETs Based Thereon (Published on July 28)

      According to information released by the China National Intellectual Property Administration (CNIPA), Xidian University has filed a patent application titled “An Interface Engineering Method for Gallium Oxide-Based Semiconductor Devices and Semiconductor Structures and Gallium Oxide MOSFETs Based Thereon”, with publication number CN122476648A and application number 2026105930245.

      The invention discloses an interface engineering method for gallium oxide-based semiconductor devices, as well as semiconductor structures and Ga₂O₃ MOSFETs based on the proposed approach. The technology belongs to the field of wide-bandgap semiconductor devices.

      The method includes providing a semiconductor structure with a gallium oxide surface; forming a silicon-rich layer on the Ga₂O₃ surface; depositing a silicon-containing oxide layer on the silicon-rich layer; and performing thermal treatment in an oxygen-containing atmosphere. During this process, interfacial reactions occur among the silicon-rich layer, silicon-containing oxide layer, and gallium oxide surface, forming a transition interfacial layer between the Ga₂O₃ surface and the silicon-containing oxide layer. This transition layer serves as the gate dielectric interface for Ga₂O₃-based semiconductor devices.

      By taking advantage of the large conduction band offset between silicon oxide and gallium oxide, the proposed structure can effectively suppress gate leakage current. Meanwhile, the transition interfacial layer reduces interface defects and border traps introduced by direct heterointerfaces, thereby improving interface quality and gate dielectric reliability in Ga₂O₃ MOSFETs.

03 Voltage-Enhanced Gallium Oxide Enhancement-Mode FINFET Device (Published on July 28)

      According to information released by the China National Intellectual Property Administration (CNIPA), Jiangsu Xin Chang Zheng Microelectronics Group Co., Ltd. has filed a patent application titled “Voltage-Enhanced Gallium Oxide Enhancement-Mode FINFET Device”, with publication number CN122476637A and application number 2026105807471.

      The invention relates to a gallium oxide FINFET device, particularly an enhancement-mode FINFET structure designed to improve voltage-blocking capability. According to the proposed technical solution, the Ga₂O₃ FINFET device includes a fin structure unit, which at least comprises a gallium oxide channel region.

      A p-type oxide unit is embedded within the gallium oxide channel region, forming a heterojunction interface between the p-type oxide unit and the Ga₂O₃ channel region. In the cross-sectional structure of the Ga₂O₃ FINFET device, the p-type oxide unit is distributed along the depth direction of the gallium oxide channel region.

      The proposed design can enhance the breakdown voltage capability of Ga₂O₃ FINFET devices while improving the stability and reliability of enhancement-mode operation.

04 Gradient Composite Thermal Field Structure for Gallium Oxide Single-Crystal Pulling Growth and Growth Method Thereof (Published on July 31)

      According to information released by the China National Intellectual Property Administration (CNIPA), Institute of Semiconductors, Guangdong Academy of Sciences has filed a patent application titled “Gradient Composite Thermal Field Structure for Gallium Oxide Single-Crystal Pulling Growth and Growth Method Thereof”, with publication number CN122484897A and application number 2026109281978.

      The invention discloses a gradient composite thermal field structure for the pulling growth of gallium oxide single crystals, as well as a corresponding gallium oxide single-crystal growth method. The thermal field structure includes a lower insulation assembly and an upper insulation assembly. The lower insulation assembly adopts a gradient combination of an insulation framework, ultra-high-temperature insulating components, a high-strength insulating base, and vibration-resistant insulation fillers. The thermal conductivity of the insulation framework and vibration-resistant fillers is higher than that of the ultra-high-temperature insulating components, forming a radial gradient insulation layer. The upper insulation assembly employs two coaxially arranged layers of high-strength insulating components with an air gap between them, creating a structurally enhanced high-performance insulation layer. The invention also provides a raw material pretreatment process, in which dense gallium oxide ceramic bodies are prepared through cold isostatic pressing and high-temperature calcination. The proposed technology enables the stable growth of large-size gallium oxide single crystals, providing a potential pathway for improving the scalability and reliability of gallium oxide crystal growth.

05 HVPE Thick-Drift-Layer High-Voltage Vertical Schottky Diode and Epitaxial Fabrication Process Thereof (Published on July 31)

      According to information released by the China National Intellectual Property Administration (CNIPA), Beijing Changlong Zhixin Semiconductor Co., Ltd. has filed a patent application titled “HVPE Thick-Drift-Layer High-Voltage Vertical Schottky Diode and Epitaxial Fabrication Process Thereof”, with publication number CN122497085A and application number 2026109106729.

      The invention discloses a high-voltage vertical Schottky diode based on HVPE-grown thick drift layers and its epitaxial fabrication process, belonging to the field of semiconductor power devices. The proposed device uses an n-type heavily doped β-Ga₂O₃ single-crystal substrate as the foundation. An n-type thick drift layer is grown on the substrate using the halide vapor phase epitaxy (HVPE) process. The structure can further incorporate optimization strategies such as hybrid HVPE/MOCVD epitaxy, gradient doping, pulsed doping, or low-doped transition layers to improve electric-field distribution. A Pt/Au Schottky anode is fabricated on the drift layer surface, while a Ti/Al/Au ohmic cathode is formed on the backside of the substrate followed by rapid thermal annealing. In addition, a mesa-etched composite passivation layer or field-plate-based electric-field termination structure is introduced at the anode edge to enhance device reliability. By fully utilizing the high-speed epitaxial growth capability of HVPE, combined with thick drift layers and advanced edge termination technologies, the invention achieves high-voltage β-Ga₂O₃ Schottky diodes with voltage ratings of 6–12 kV. The proposed devices feature high breakdown voltage, low on-resistance, and efficient, controllable epitaxial fabrication processes, providing a potential technical route for next-generation high-voltage β-Ga₂O₃ power devices.

06 Gallium Oxide Power Diode with Single-Event Radiation Tolerance and Fabrication Method Thereof (Published on July 31)

      According to information released by the China National Intellectual Property Administration (CNIPA), University of Science and Technology of China (USTC) has filed a patent application titled “Gallium Oxide Power Diode with Single-Event Radiation Tolerance and Fabrication Method Thereof”, with publication number CN122497084A and application number 2026106040950.

      The invention relates to the field of semiconductor devices, particularly a gallium oxide power diode with enhanced resistance to single-event radiation effects and its fabrication method. The proposed gallium oxide power diode comprises a vertically stacked structure including a cathode, gallium oxide substrate layer, gallium oxide epitaxial layer, nickel oxide layer, dielectric layer, and anode. Multiple trenches are formed on the upper surface of the gallium oxide epitaxial layer, and the nickel oxide layer covers the bottom and sidewalls of each trench. The nickel oxide layer consists of a first nickel oxide layer and a second nickel oxide layer. The dielectric layer is arranged on the upper surface of the second nickel oxide layer and wraps around its outer side, forming multiple first recess structures. The dielectric layer also contains multiple second recess structures. The anode is formed on the upper surface of the dielectric layer and fully fills both the first and second recess structures.

      The proposed device utilizes a junction termination extension (JTE) structure to shift the radiation-sensitive region of the device from the anode edge toward the junction region. Meanwhile, the trench structure introduced in the junction region enables efficient extraction of radiation-induced holes, thereby improving the single-event burnout (SEB) breakdown voltage of gallium oxide power diodes and enhancing their radiation reliability for extreme-environment applications.

07 Gallium Oxide Power Device with Electric-Field and Thermal-Field Co-Optimization Enabled by Nanocrystalline Diamond Passivation and Fabrication Method Thereof (Published on July 31)

      According to information released by the China National Intellectual Property Administration (CNIPA), Xidian University has filed a patent application titled “Gallium Oxide Power Device with Electric-Field and Thermal-Field Co-Optimization Enabled by Nanocrystalline Diamond Passivation and Fabrication Method Thereof”, with publication number CN122497366A and application number 202610575044X.

      The invention discloses a gallium oxide power device featuring electric-field and thermal-field co-optimization through nanocrystalline diamond passivation, along with its fabrication method. The technology mainly addresses several challenges in existing Ga₂O₃ devices, including severe heat accumulation in the gate-drain region, surface electric-field crowding, limited functionality of top functional layers, and the impact of large-area coverage structures on gate control performance.

      The proposed device consists of a substrate, buffer layer, gallium oxide active layer, MOS gate dielectric, top p-type nanocrystalline diamond passivation thermal-spreading layer, drain-side spacer region, second passivation layer, thermal-spreading metal layer, and metal electrodes.

      The channel region retains the MOS gate dielectric, while a localized contact-type p-type nanocrystalline diamond passivation thermal-spreading layer is introduced on the surface of the n-type drift region between the drain-side gate edge and the drain electrode. A second passivation layer and an independent thermal-spreading metal layer are subsequently formed above the diamond layer.

      By integrating electric-field regulation and thermal management, the proposed structure can effectively suppress electric-field concentration and localized heat accumulation, thereby significantly improving the stability, reliability, and operational performance of gallium oxide power devices.

      In addition to patents focusing on gallium oxide materials, several patents published this week also involve the application of gallium oxide as a functional material in other fields, which are provided for readers’ reference.

01 Composite Catalyst, Preparation Method Thereof, and Application in Low-Carbon Olefin Production from Syngas (Published on July 31)

      According to information released by the China National Intellectual Property Administration (CNIPA), Ningxia Institute of Metrology and Quality Inspection has filed a patent application titled “Composite Catalyst, Preparation Method Thereof, and Application in Low-Carbon Olefin Production from Syngas”, with publication number CN122479806A and application number 2026107160004.

      The invention provides a composite catalyst, its preparation method, and its application in the synthesis of low-carbon olefins from syngas, belonging to the field of low-carbon olefin production technologies.

      The proposed catalyst combines a composite metal oxide with an SAPO-34 molecular sieve. During the syngas-to-methanol conversion process, the ternary metal oxide system plays multiple roles: zinc oxide (ZnO₂) serves as the structural framework and CO activation center; gallium oxide (Ga₂O₃) promotes the dissociation and activation of H₂; while aluminum oxide (Al₂O₃) acts as a key promoter to further regulate the catalyst’s electronic structure and acidic active sites.

      Through this synergistic design, the catalyst achieves improved activity, selectivity, and stability for syngas-to-methanol conversion under relatively mild reaction conditions. Subsequently, the generated methanol intermediates undergo dehydration and C–C coupling reactions on the surface of the low-Si/Al SAPO-34 molecular sieve, enabling the highly selective production of light olefins.

      The proposed composite catalyst provides a potential pathway for enhancing the efficiency and selectivity of low-carbon olefin synthesis from syngas, supporting the development of cleaner chemical conversion technologies.