Patents
【Patents】Gallium Oxide Patent Weekly Report (Issue 6, August)
日期：2026-08-14阅读：64
Introduction
To further strengthen information exchange within the gallium oxide industry and help stakeholders stay informed of the latest technological developments, the Asian Gallium Oxide Alliance (AGOA) has launched the Gallium Oxide Patent Weekly column. This series will continuously compile and publish newly disclosed patent applications and technological advances in the gallium oxide field.
As an important indicator of technological innovation, patents reflect R&D trends and strategic layout across the industrial chain. This column focuses on crystal growth, material preparation, defect engineering, device development, process optimization, and emerging applications, providing enterprises, universities, and research institutes with insights into technology trends while supporting the continued development of the gallium oxide industry.
This sixth issue reviews gallium oxide-related patent applications published during the first week of August 2026 (August 3 – August 9).
1.ZnO Thin Film, Mg-Doped ZnO Thin Film, Preparation Method and Applications Thereof, and Ultraviolet Photodetector (Published on 8.4)
According to information from the China National Intellectual Property Administration (CNIPA), Hubei University has filed a patent application titled “ZnO Thin Film, Mg-Doped ZnO Thin Film, Preparation Method and Applications Thereof, and Ultraviolet Photodetector”, with publication number CN122514075A and application number 202610717677X.
The invention provides a ZnO thin film, Mg-doped ZnO thin film, preparation method and applications thereof, as well as an ultraviolet photodetector. Based on the low-cost sol-gel method, the researchers developed a three-step strategy combining annealing-process optimization, Mg doping control, and heterostructure engineering to address key issues in ZnO thin films, including abundant oxygen-vacancy defects, limited crystal quality, and the performance limitations of single-material devices.
The optimized ZnO-based film was further integrated with a Ga₂O₃ substrate to fabricate a heterojunction photodetector with self-powered operation, an ultrafast response time of 65 ms, and a high detectivity of 1.47 × 10¹² Jones. The work provides a low-cost materials optimization approach and a device-design strategy for the development of high-performance ultraviolet photodetectors.
2.Solar-Blind Ultraviolet Photodetector for Light-Spot Localization Based on a Ga₂O₃–In₂Ge₂O₇ Crossed Microwire Heterojunction and Preparation Method Thereof (Published on 8.4)
According to information from the China National Intellectual Property Administration (CNIPA), Beijing University of Technology has filed a patent application titled “Solar-Blind Ultraviolet Photodetector for Light-Spot Localization Based on a Ga₂O₃–In₂Ge₂O₇ Crossed Microwire Heterojunction and Preparation Method Thereof”, with publication number CN122514051A and application number 202610646808X.
The invention relates to solar-blind ultraviolet photodetection technology. The photodetector comprises a substrate, crossed Ga₂O₃ microwires and In₂Ge₂O₇ microwires, and electrodes arranged at both ends of the microwires.
A crossed microwire heterojunction is fabricated using a mechanical transfer method, allowing the Ga₂O₃ and In₂Ge₂O₇ microwires to be precisely positioned across each other. Under a constant bias, the locally enhanced electric field in the heterojunction region enables efficient collection of photogenerated carriers primarily at the crossing point, while the device exhibits a relatively low photoresponse when illuminated away from the crossing point. This spatially localized photoresponse enables light-spot position localization.
By taking advantage of the intrinsic solar-blind absorption characteristics of Ga₂O₃ and In₂Ge₂O₇ together with the spatial localization of photocurrent enabled by the crossed heterostructure, the proposed device offers high spatial resolution, a simple structure, flexible-integration potential, and high localization accuracy, providing a potential approach for solar-blind ultraviolet light-spot localization.
3.A Horizontal AlN-Based Insulated-Gate Heterojunction Transistor and Preparation Method Thereof (Published on 8.4)
According to information from the China National Intellectual Property Administration (CNIPA), Xidian University has filed a patent application titled “A Horizontal AlN-Based Insulated-Gate Heterojunction Transistor and Preparation Method Thereof”, with Publication No. CN122514012A and Application No. 2026106346449.
The present application provides a horizontal AlN-based insulated-gate heterojunction transistor and a preparation method thereof. The transistor comprises an N-type gallium oxide epitaxial layer located on a P-type AlN single-crystal substrate; a P-type AlN epitaxial region formed on the N-type gallium oxide epitaxial layer and not completely covering the layer; an N+ heavily doped contact region and a heavily doped P-type region formed in the N-type gallium oxide epitaxial layer; a gate dielectric layer covering the P-type AlN epitaxial region; a source metal formed on the N+ heavily doped contact region; a drain metal formed on the heavily doped P-type region; and a gate metal formed on the gate dielectric layer.
The invention combines a selectively epitaxially grown P-type AlN region with ion-implanted doped regions, thereby circumventing the process bottleneck associated with the difficult activation of p-type dopants in AlN. Meanwhile, the use of an atomic layer deposition (ALD) gate dielectric layer significantly reduces the interface-state density, effectively suppresses current collapse, and improves the gate control capability and long-term reliability of the device.
4.Ga₂O₃ U-Gate Vertical Transistor Based on Phosphorus Ion Implantation and Preparation Method Thereof (Published on 8.4)
According to information from the China National Intellectual Property Administration (CNIPA), Xidian University has filed a patent application titled “Ga₂O₃ U-Gate Vertical Transistor Based on Phosphorus Ion Implantation and Preparation Method Thereof”, with Publication No. CN122514004A and Application No. 202610464480X.
The invention discloses a Ga₂O₃ U-gate vertical transistor based on phosphorus ion implantation and a preparation method thereof. Phosphorus ions are implanted into a lightly doped n-type Ga₂O₃ drift region to form a current-blocking region. Silicon ions are then implanted into the upper surface of the current-blocking region to form an ohmic contact layer. Subsequently, a U-shaped gate trench penetrating through the ohmic contact layer and current-blocking region and extending into part of the lightly doped n-type Ga₂O₃ drift layer is formed by etching. A source electrode, drain electrode, gate dielectric layer, and gate electrode are then formed to obtain the Ga₂O₃ U-gate vertical transistor.
The proposed transistor uses phosphorus ion implantation to form the current-blocking layer, thereby regulating the current conduction path. This approach enables the fabrication of an enhancement-mode Ga₂O₃ vertical transistor with low on-resistance without relying on p-type doping of Ga₂O₃. As a result, the device's current-driving capability is improved while the device fabrication cost is reduced.
5.Semiconductor Device (Published on 8.4)
According to information from the China National Intellectual Property Administration (CNIPA), Shindengen Electric Mfg.Co.Ltd has filed a patent application titled “Semiconductor Device”, with Publication No. CN122515055A and Application No. 2024800713320.
The present invention provides a semiconductor device (100) comprising: an N-type gallium oxide crystal substrate (200); an electrode portion (400) disposed on the upper surface of the gallium oxide crystal substrate; a P-type oxide semiconductor portion (210) disposed on the lower surface of the gallium oxide crystal substrate and in contact with the electrode portion; a high-resistance layer portion (610) disposed on the lower surface of the gallium oxide crystal substrate and on the upper surface of the P-type oxide semiconductor portion; and an electrode portion (300) disposed on the upper surface of the gallium oxide crystal substrate and electrically isolated from the electrode portion (400), the P-type oxide semiconductor portion, and the high-resistance layer portion.
6.Method for Low-Temperature Growth of Gallium Oxide and Heterostructures Thereof (Published on 8.7)
According to information from the China National Intellectual Property Administration (CNIPA), Xidian University has filed a patent application titled “Method for Low-Temperature Growth of Gallium Oxide and Heterostructures Thereof”, with Publication No. CN122522395A and Application No. 2026108807327.
The present invention provides a method for low-temperature growth of gallium oxide and heterostructures thereof. The method comprises placing a substrate in a reaction chamber and heating it to a target temperature, while activating a microwave plasma source at the outlet of the atomization chamber to act on the aerosol droplets, thereby creating an activated environment. Depending on the desired crystal phase, either a direct-growth mode or an assisted-conversion growth mode is selected for the deposition process to form a gallium oxide/oxide heterostructure.
In the direct-growth mode, a gallium source is atomized and activated at the source before an epitaxial gallium oxide layer is grown, followed by deposition of an oxide layer. In the assisted-conversion growth mode, an initial gallium oxide layer is first deposited, followed by low-energy ion bombardment to induce a solid-state phase transformation and obtain the target crystal phase, after which an oxide layer is deposited. Finally, atomization is stopped and the plasma source is turned off. After cooling, the gallium oxide/oxide heterostructure thin-film sample is removed.
The invention enables high-quality epitaxial growth at significantly reduced process temperatures, while avoiding low-temperature amorphization and enabling precise control over the crystal phase of gallium oxide, thereby providing a wide process window for the controlled fabrication of heterostructures.
7.Synaptic Device Based on a Gallium Oxide–Tungsten Disulfide Heterojunction and Preparation Method Thereof (Published on 8.7)
According to information from the China National Intellectual Property Administration (CNIPA), Jimei University has filed a patent application titled “Synaptic Device Based on a Gallium Oxide–Tungsten Disulfide Heterojunction and Preparation Method Thereof”, with Publication No. CN122535157A and Application No. 202610661785X.
The present invention provides a synaptic device based on a gallium oxide–tungsten disulfide (Ga₂O₃–WS₂) heterojunction and a preparation method thereof. In response to electrical signal stimulation, the synaptic device successfully simulates various forms of biological synaptic plasticity, including paired-pulse facilitation (PPF) and paired-pulse depression (PPD), spike-rate-dependent plasticity (SRDP), spike-number-dependent plasticity (SNDP), spike-voltage-dependent plasticity (SVDP), plasticity associated with the transition from short-term memory (STM) to long-term memory (LTM), as well as long-term potentiation (LTP) and long-term depression (LTD).
In addition, the synaptic device achieves low-power operation, demonstrating its potential for energy-efficient neuromorphic computing applications.
8.High-Voltage Enhancement-Mode Ga₂O₃ FINFET Power Device (Published on 8.7)
According to information from the China National Intellectual Property Administration (CNIPA), Jiangsu Xin Changzheng Microelectronics Group Co., Ltd. has filed a patent application titled “High-Voltage Enhancement-Mode Ga₂O₃ FINFET Power Device”, with Publication No. CN122534915A and Application No. 2026105807467.
The present invention relates to a high-voltage enhancement-mode Ga₂O₃ FINFET power device. The device comprises a FIN structure unit, which at least includes a Ga₂O₃ channel body. The Ga₂O₃ channel body comprises at least a first channel segment arranged in a longitudinal direction and a second channel segment disposed on one side of and correspondingly connected to the first channel segment. A first inter-segment transition region is provided at the junction between the second channel segment and the first channel segment. The first inter-segment transition region is configured to form at least a first lateral region, while the remaining region of the second channel segment, excluding the portion corresponding to the first inter-segment transition region, forms a first longitudinal region similar to that of the first channel segment.
Through this configuration, the Ga₂O₃ channel body is designed to achieve a three-dimensional electric-field distribution that satisfies the RESURF (Reduced Surface Field) technology.
The invention enables stable enhancement-mode operation and increased breakdown voltage, thereby improving the reliability of Ga₂O₃ FINFET devices for industrial applications.
9.Optically Controlled Semiconductor Switch and Preparation Method Thereof (Published on 8.7)
According to information from the China National Intellectual Property Administration (CNIPA), Shenzhen Pinghu Laboratory has filed a patent application titled “Optically Controlled Semiconductor Switch and Preparation Method Thereof”, with Publication No. CN122534973A and Application No. 2026105366553.
The present invention discloses an optically controlled semiconductor switch and a preparation method thereof. The optically controlled semiconductor switch comprises a heterogeneous integrated structure, which includes an intrinsic-type (i-type) gallium oxide layer and a p-type diamond layer disposed on one side of the i-type gallium oxide layer. The p-type diamond layer and the i-type gallium oxide layer form a p-i heterojunction.
A first electrode is disposed on the side of the i-type gallium oxide layer opposite the p-type diamond layer and forms an ohmic contact with the i-type gallium oxide layer, allowing light to be irradiated onto the i-type gallium oxide layer from the first-electrode side. A second electrode is disposed on the side of the p-type diamond layer opposite the i-type gallium oxide layer and forms an ohmic contact with the p-type diamond layer.
When light is irradiated onto the i-type gallium oxide layer, the optically controlled semiconductor switch can be configured to switch from a high-resistance OFF state to a low-resistance ON state.
The optically controlled semiconductor switch can significantly improve the optical response speed and optical triggering efficiency, while addressing the performance degradation and reliability issues caused by heat accumulation in gallium oxide materials under high-power operation.
10.Enhancement-Mode Ga₂O₃ Transistor Based on a Heteroepitaxial Substrate and Fabrication Method Thereof (Published on 8.7)
According to information from the China National Intellectual Property Administration (CNIPA), Southwest Jiaotong University has filed a patent application titled “Enhancement-Mode Ga₂O₃ Transistor Based on a Heteroepitaxial Substrate and Fabrication Method Thereof”, with Publication No. CN122534913A and Application No. 2026104873175.
The present invention belongs to the field of semiconductor devices and relates to an enhancement-mode gallium oxide transistor based on a heteroepitaxial substrate and a fabrication method thereof. The method specifically comprises the following steps: Step 1, preparing a heteroepitaxial substrate; Step 2, epitaxially growing a gallium oxide material layer on the heteroepitaxial substrate by metal-organic chemical vapor deposition (MOCVD); Step 3, etching the gallium oxide material layer to form a gate trench; Step 4, depositing a gate dielectric stack containing a high-k dielectric material on the gallium oxide material layer with the gate trench formed therein; and Step 5, forming a gate electrode on the gate dielectric stack and fabricating source and drain electrodes to obtain the enhancement-mode gallium oxide transistor.
The invention reduces the impact of the quality of the Ga₂O₃ material grown by MOCVD on the heteroepitaxial substrate by modifying the dielectric material in contact with the gallium oxide, specifically by employing a high-k gate insulating material. This approach mitigates non-ideal effects associated with the relatively high interface-state density of MOCVD-grown Ga₂O₃ on heteroepitaxial substrates.
11.Gallium Oxide Schottky Diode with a Composite Termination Structure (Published on 8.7)
According to information from the China National Intellectual Property Administration (CNIPA), University of Electronic Science and Technology of China (UESTC) has filed a patent application titled “Gallium Oxide Schottky Diode with a Composite Termination Structure”, with Publication No. CN122534888A and Application No. 202511435288X.
The present invention belongs to the field of power semiconductor technology and relates to a gallium oxide Schottky diode with a composite termination structure. To optimize the electric-field distribution in the termination region of gallium oxide power diodes and thereby improve the device's voltage withstand capability, the invention proposes a composite termination structure consisting of a mesa termination, a thermal oxidation region, and a nitrogen-ion-implanted region.
During forward conduction, the N-type gallium oxide drift region retained between the composite termination regions forms a Schottky contact with the anode metal, enabling the device to achieve a low forward voltage drop and low specific on-resistance.
During reverse blocking, the mesa termination promotes the expansion of the depletion region into the gallium oxide bulk. The thermal oxidation region reduces the carrier concentration in the drift region, thereby forming an equivalent high-low junction with the drift region. Meanwhile, the nitrogen-ion-implanted region forms a high-resistance layer that alleviates the electric-field peak at the bottom corner of the mesa. These three components together form a graded composite termination structure, optimizing the electric-field distribution and enabling high-voltage blocking capability.
As a result, the gallium oxide device of the invention achieves low leakage current, low specific on-resistance, and high breakdown voltage.
