【Patenes】Gallium Oxide Patent Weekly Report (Issue 10, September)

      To further strengthen information exchange within the gallium oxide industry and help stakeholders stay informed of the latest technological developments, the Asian Gallium Oxide Alliance (AGOA) has launched the Gallium Oxide Patent Weekly column. This series will continuously compile and publish newly disclosed patent applications and technological advances in the gallium oxide field.

      As an important indicator of technological innovation, patents reflect R&D trends and strategic layout across the industrial chain. This column focuses on crystal growth, material preparation, defect engineering, device development, process optimization, and emerging applications, providing enterprises, universities, and research institutes with insights into technology trends while supporting the continued development of the gallium oxide industry.

      This tenth issue reviews gallium oxide-related patent applications published during the first week of September 2026 (August 31–September 6).

01 Ga₂O₃ Photodetector, Preparation Method and Application (Published September 1)

      According to information from the China National Intellectual Property Administration (CNIPA), Suzhou Institute of Nano-Tech and Nano-Bionics, Chinese Academy of Sciences has filed a patent application entitled “Ga₂O₃ Photodetector, Preparation Method and Application.” The publication number is CN122679707A, and the application number is 2026111643341.

      The application discloses a Ga₂O₃ photodetector, along with its preparation method and applications. The Ga₂O₃ photodetector includes a high-work-function metal barrier layer, a Ga₂O₃ layer, and a channel layer sequentially stacked on one another. It also includes a bottom electrode electrically connected to a Ge film while being electrically isolated from the high-work-function metal barrier layer and the Ga₂O₃ layer, as well as a top electrode formed on the channel layer. The channel layer includes the Ge film.

      The device adopts a structural design that separates the light-absorption region from the carrier-drift region. In this architecture, the Ga₂O₃ layer serves solely as the light-absorbing layer, while the current is primarily distributed through the Ge channel. This effectively alleviates the limitations imposed by the low carrier mobility and hole self-trapping effect of Ga₂O₃. At the same time, the introduction of a thin high-work-function metal barrier layer allows the device to fully leverage the high-speed electron transport capability of Ge while avoiding the adverse impact of low hole mobility on device response. Ultimately, the proposed structure enables a high-speed, high-sensitivity solar-blind ultraviolet (UV) photodetector.

02 Alloy–Liquid Metal Composite Material Design Method Based on Energy Evaluation and Electronic-Structure Characteristics (Published September 1)

      According to information from the China National Intellectual Property Administration (CNIPA), Beijing Institute of Technology has filed a patent application entitled “Alloy–Liquid Metal Composite Material Design Method Based on Energy Evaluation and Electronic-Structure Characteristics.” The publication number is CN122677014A, and the application number is 2026107978501.

      The invention discloses a design method for alloy–liquid metal composite materials based on energy evaluation and electronic-structure characteristics. The method uses density functional theory (DFT) to construct heterointerface models between the (111) surface of cobalt–nickel alloys (CoₓNiᵧ) with different atomic ratios and Ga₂O₃. By quantitatively calculating the surface energy of the alloy and interfacial adsorption energy, the method establishes evaluation criteria and identifies the optimal alloy composition that balances thermodynamic stability with interfacial chemical adsorption strength.

      Through Bader charge analysis, differential charge-density analysis, and projected density of states (PDOS) analysis, the method clarifies the extent of charge transfer and orbital hybridization at the solid–liquid interface, establishing the bonding mechanism between the metal and oxide at the atomic scale. It further simulates the interfacial formation reaction pathways under different oxygen partial pressures and predicts the evolution of interfacial bonding configurations based on Gibbs free-energy changes.

      The invention achieves a balance between interfacial bonding strength and liquid-metal fluidity, providing a design basis for constructing solid–liquid synergistic conductive networks with high dynamic stability and continuity.

03 Novel Diamond-Based Light-Enabled Gate-Controlled Transistor and Preparation Method (Published September 1)

      According to information from the China National Intellectual Property Administration (CNIPA), Zhengzhou University has filed a patent application entitled “Novel Diamond-Based Light-Enabled Gate-Controlled Transistor and Preparation Method.” The publication number is CN122679728A, and the application number is 2026107897082.

      The invention relates to a novel diamond-based light-enabled gate-controlled transistor and its preparation method for optoelectronic integrated devices. First, a diamond sample is subjected to oxygen-plasma surface etching by microwave plasma chemical vapor deposition (MPCVD), followed by hydrogenation treatment. A gold layer is then deposited on the sample surface. Photoresist is subsequently spin-coated, patterned, developed, and treated with oxygen plasma to form a hydrogen-terminated channel, with Au serving as the source and drain electrodes.

      Meanwhile, a mixed precursor solution containing tin-doped gallium oxide is prepared. A gold thin film is deposited on a sapphire substrate by magnetron sputtering. The substrate is then inverted and positioned above the precursor solution before being introduced into a CVD tube furnace for Ga₂O₃ dielectric-layer deposition, enabling the growth of tin-doped Ga₂O₃ microwires on the substrate.

      Finally, micro/nanotransfer technology is used to precisely align the microwires with the hydrogen-terminated channel, followed by the application of silver paste to form the Ag gate electrode. Under solar-blind UV illumination, the resulting light-enabled gate-controlled transistor exhibits gate-tunable positive and negative photoresponse characteristics, enabling an integrated “detection–logic–communication” functionality.

04 Ga₂O₃ Thin Film Based on a Heterogeneous Substrate and Preparation Method and Application (Published September 4)

      According to information from the China National Intellectual Property Administration (CNIPA), Suzhou Gusu Laboratory of Materials has filed a patent application entitled “Ga₂O₃ Thin Film Based on a Heterogeneous Substrate and Preparation Method and Application.” The publication number is CN122687351A, and the application number is 202611177078X.

      The invention relates to the preparation of Ga₂O₃ thin films. The Ga₂O₃ thin film based on the heterogeneous substrate comprises, from bottom to top, a substrate, an AlN crystal-seed layer, a porous AlN epitaxial layer, and a Ga₂O₃ thin film arranged in a stacked configuration. The surface of the porous AlN epitaxial layer adjacent to the Ga₂O₃ thin film contains non-through holes extending along the thickness direction.

      The invention uses the AlN crystal-seed layer and porous AlN epitaxial layer in combination as a heterogeneous substrate for the growth of the Ga₂O₃ thin film. The porous structure on the surface of the AlN epitaxial layer promotes a higher degree of dislocation annihilation within the Ga₂O₃ film, effectively reducing stress during epitaxial growth and mitigating lattice mismatch. As a result, the growth quality of the Ga₂O₃ thin film can be improved.

05 Manufacturing Method for a Ga₂O₃ PN-Junction Power Diode Device (Published September 4)

      According to information from the China National Intellectual Property Administration (CNIPA), the 13th Research Institute of China Electronics Technology Group Corporation (CETC) has filed a patent application entitled “Manufacturing Method for a Ga₂O₃ PN-Junction Power Diode Device.” The publication number is CN122699319A, and the application number is 2026108351992.

      The invention provides a manufacturing method for a Ga₂O₃ PN-junction power diode and relates to the field of semiconductor device technology. The method is implemented based on a basic structure consisting, from bottom to top, of a cathode, substrate layer, epitaxial layer, and dielectric mask layer. First, photolithography and etching are used to form a groove extending through the dielectric mask layer and the upper portion of the epitaxial layer. A p-type heterolayer is then grown over the groove and the surface of the epitaxial layer, followed by fabrication of the anode. Dry etching is subsequently used to remove the excess p-type heterolayer, after which the dielectric mask layer and residual material above it are removed. This results in a diode device in which the p-type heterolayer and anode are retained only within the groove.

      By embedding the p-type heterolayer into a groove in the Ga₂O₃ epitaxial layer, the method forms a PN-junction-like structure without requiring p-type doping of Ga₂O₃. This fundamentally avoids the technical challenges associated with p-type doping in Ga₂O₃ and can significantly increase the device breakdown voltage while improving its power figure of merit (PFOM).

06 Tungsten-Doped Amorphous Ga₂O₃ Thin Film, Back-Gate Thin-Film Transistor, and Preparation Method (Published September 4)

      According to information from the China National Intellectual Property Administration (CNIPA), Jimei University has filed a patent application entitled “Tungsten-Doped Amorphous Ga₂O₃ Thin Film, Back-Gate Thin-Film Transistor, and Preparation Method.” The publication number is CN122699363A, and the application number is 2026107552759.

      The invention discloses a tungsten-doped amorphous Ga₂O₃ thin film, a back-gate thin-film transistor based on the thin film, and a preparation method, and relates to the field of advanced semiconductor materials and devices. In the tungsten-doped amorphous Ga₂O₃ thin film, tungsten is uniformly incorporated into the amorphous Ga₂O₃ matrix. During preparation, pre-calcined Ga₂O₃ powder and WO₃ powder are mixed at a specified ratio, compacted, and then sintered to form a composite target. The target is subsequently used for deposition onto a room-temperature substrate by electron-beam evaporation.

      The back-gate thin-film transistor uses the tungsten-doped amorphous Ga₂O₃ thin film as its channel layer and Mg₉₀Al₁₀ alloy as the source/drain electrode material, forming ohmic contacts with the Ga₂O₃ active region.

      By introducing donor levels into amorphous Ga₂O₃ through tungsten doping, the invention significantly increases the carrier concentration and mobility. Meanwhile, the use of Mg₉₀Al₁₀ alloy electrodes enables low-resistance ohmic contact with the channel layer, reducing manufacturing costs. The approach addresses key technical challenges associated with the low electrical conductivity and limited tunability of amorphous Ga₂O₃, as well as the high cost of forming ohmic contacts in devices based on the material.