【International Papers】Monolithic β-Ga₂O₃ NMOS IC based on heteroepitaxial E-mode MOSFETs

      Recently, the research team of King Abdullah University of Science and Technology in Saudi Arabia published an article titled Monolithic in the scientific journal AIP Publishing β- Paper article on Ga₂O₃ NMOS IC based on heteroepitaxial E-mode MOSFETs.

ABSTRACT

      In this Letter, we report on a monolithically integrated β-Ga₂O₃ NMOS inverter integrated circuit (IC) based on heteroepitaxial enhancement mode (E-mode) β-Ga₂O₃ metal-oxide-semiconductor field-effect transistors on low-cost sapphire substrates. A gate recess technique was employed to deplete the channel for E-mode operation. The E-mode devices showed an on-off ratio of ∼10⁵ with a threshold voltage of 3 V. In comparison, control devices without the gate recess exhibited a depletion mode (D-mode) with a threshold voltage of −−3.8 V. Furthermore, depletion-load NMOS inverter ICs were fabricated by monolithically integrating D- and E-mode transistors on the same substrate. These NMOS ICs demonstrated inverter logic operation with a voltage gain of 2.5 at V_DD = 9 V, comparable with recent GaN and other wide-bandgap semiconductor-based inverters. This work lays the foundation for heteroepitaxial low-cost and scalable β-Ga₂O₃ ICs for monolithic integration with (ultra)wide bandgap Ga₂O₃ power devices.

FIG 1.Cross-sectional view of (a) the recessed gate. 3D schematics of (b) non-recessed and (c) recessed gates. (d) Fabrication process flow. (e) Scanning electron microscopy (SEM) top view of the β-Ga₂O₃ MOSFETs.

FIG 2. β-Ga₂O₃ film characterization: (a) x-ray diffraction and (b) atomic force microscopy (AFM) image. AFM image of (c) the recess profile, (c-inset) recess depth, and(d) surface topography (inside recess). Scanning transmission electron microscopy (STEM) image of (e) the sidewall (highlighting a recess depth of 11 nm) and (f) the bottom facet of gate recess.

FIG 3. Transfer (logarithmic and linear) and output characteristics, respectively, (a) and (b) non-recessed and (c) and (d) recessed MOSFETs at different drain-source (V_DS) and gate-source voltages (V_GS). Linear transfer behavior is at V_DS = 5 V, shown in (a) and (c).