【Domestic News】USTC has made significant progress in the field of power electronics

      Recently, Five papers from Professor Long Shibing's research group at the School of Microelectronics, China University of Science and Technology were selected for the 36th IEEE International Symposium on Power Semiconductor Devices and ICs (IEEE ISPSD). IEEE ISPSD is the most influential and largest top-level international academic conference in the field of power devices and is considered the Olympic conference in the field of power semiconductor devices and integrated circuits, IEEE ISPSD 2024 was held in Germany from June 2 to June 6 this year. China University of Science and Technology School of Microelectronics Zheng Zhe Yang special professor and Xu Guangwei special researcher led the team to participate in the event.

Figure 1. Group photo of participants: Professor Zheng Zhe Yang (second from right), Researcher Xu Guangwei (first from right).

      The work of the five selected papers is as follows:

      1、Identification and suppression methods for key defect of Gallium Oxide

      In order to prepare high withstand voltage Gallium Oxide Schottky Barrier Diode (SBD) and take advantage of Gallium Oxide materials, high performance power diodes need to epitaxial growth of low doping concentration epitaxial layer on the substrate as the pressure region. Halide Vapor Phase Epitaxy (HVPE) has become an important method for Gallium Oxide epitaxy growth by combining the advantages of growth rate and crystal quality. However, due to the fast growth rate, partial disorder or holes are easy to occur in the crystal during the growth process, and these defect may have a great impact on the performance of the device. In this work, a linear lattice defect along the (010) crystal direction was identified by means of low-light microscopy (EMMI) as a key defect leading to the premature breakdown of Gallium Oxide SBD (Figure 2). The electrical characteristics of the defect region are revealed by Kelvin probe and atomic force probe. The accumulation of fixed negative charge leads to the increase of electric field, which leads to the increase of leakage and premature breakdown. In addition, high breakdown Gallium Oxide SBD was successfully prepared by high temperature oxygen annealing to repair the defect and reduce the number of defect on the wafer. The research results are summarized as "The Role of Line-shaped Defects in Premature Breakdown of β-Ga₂O₃ Power Diode and Suppression by Oxygen. The research results have been published in IEEE ISPSD 2024 and reported on the field, and the first author is Jinyang Liu, a doctoral student.

FIG. 2. Surface morphology and electrical characteristics of linear defect (a-c), (d) breakdown characteristics of the device after defect improved by oxygen annealing, and (e) comparison of the leakage mechanism of the device before and after optimization.

      2、Low leakage, high withstand voltage β-Ga₂O₃ heterojunction barrier schottky diode

      In response to the problem that the Schottky junction center region of β-Ga₂O₃ SBD devices can still cause large leakage current under high electric field, the RESURF technology - junction barrier Schottky structure was introduced. p-NiO is embedded on the Schottky central surface to form a β-Ga₂O₃ HJBSD device with alternating p-n junction arrangement. Thanks to the strong RESURF effect, the β-Ga₂O₃ HJBSD device exhibited extremely low reverse leakage current of less than 1 mA/cm², and the breakdown voltage reached more than 2.7 kV. The β-Ga₂O₃ HJBSD device successfully combines the advantages of SBD and HJD devices with the excellent characteristics of low opening voltage, low leakage current and high breakdown voltage (Figure 3). The results are described as "2.7kV β-Ga₂O₃ Heterojunction Barrier Schottky Diode with Low Leakage Current < 1 mA/cm² Based upon RESURF. "Effect" is published in IEEE ISPSD 2024, with PhD student Weibing Hao as the first author.

Figure 3. (a) Schematic diagram of vertical Gallium Oxide HJBSD device structure, (b) extract specific on-resistance of SBD and HJBSDs devices, and (c) extract on-resistance of SBD and HJBSDs at forward on-voltage 2 V (before heterojunction on-conduction) and 3.5 V (after heterojunction on-conduction), respectively. (d) Comparison of reverse breakdown characteristics of SBD and HJBSDs devices.

      3、Research on high withstand voltage Gallium Oxide Schottky Barrier Diode

      In recent years, the research of Schottky Barrier Diode (SBD) based on β-Ga₂O₃ has developed rapidly and is expected to be the first to achieve commercialization. However, there is still a big gap between the actual performance of the device and the theoretical limit, and the effective edge terminal design is very important to improve the performance of the device. Mesa (Mesa) can effectively remove the cylindrical or spherical junction of the SBD edge, so that the whole device presents a relatively uniform electric field distribution. However, the distribution of high electric field on the side wall of the etched mesa, as well as the surface charge enrichment caused by dry etching, may present the risk of additional leakage current and premature breakdown. Based on this, the research group designed and prepared a high-performance β-Ga₂O₃ SBD with a composite terminal (FIG. 4). The composite terminal (MJTE) combines a mesa terminal and a graded junction terminal extension structure (JTE). The mesa design avoids the peak electric field at the anode edge, while the graded multilayer P-type nickel oxide (NiO) design further effectively regulates the gradient of the electric field distribution. Using the TCAD simulation tool, the working system investigates the relationship between the electric field distribution and NiO thickness, mesa depth and JTE length. Combined with the optimization parameters, the breakdown voltage of the actual prepared device is increased from 738 V to 2116 V, and the power superiority value (PFOM) is increased by seven times (from 81.05 to 608.35 MW/cm²). This work provides a practical and effective solution for improving the performance of β-Ga₂O₃ SBD. The results of the research are "Improved β-Ga₂O₃ Schottky Barrier Diodes Featuring p-NiO Gradual Junction Termination Extension within Mesa. Structure "was published in IEEE ISPSD 2024, with PhD student Zhao Han as the first author.

FIG. 4. (a) Schematic diagram of the designed β-Ga₂O₃ MJTE-SBD device, (b) Scanning electron microscope image of the prepared device, (c) statistical distribution results of the breakdown characteristics of the device, and (d) performance comparison between the working device and internationally reported devices.

      4、Low-gate leakage Gallium Oxide pn junction - heterojunction field effect transistor

      p-NiO based β-Ga₂O₃ heterojunction field-effect transistors show great potential in high-power and high-frequency switching applications. However, in previous studies, p-NiO based β-Ga₂O₃ heterojunction field-effect transistors had parasitic gate-source pn diodes, resulting in large gate leakage currents, prompting the need for innovative solutions. In this work, to solve the gate breakdown problem of β-Ga₂O₃ heterojunction field-effect transistor (HJFET), a novel PNJ-HJFET was successfully designed and fabricated by introducing NiOx/GaOx gate stack structure. This structure significantly increases the gate breakdown voltage to 14.2V. The PNJ-HJFET exhibits excellent stability and extremely low threshold voltage offset over a wide temperature range of 25 to 250 ° C (Figure 5). In addition, by analyzing the gate leakage characteristics, the conduction mechanism of PNJ-HJFET at different temperatures is revealed, which provides an effective solution to the gate breakdown problem of β-Ga₂O₃ HJFETs. The research results are published in IEEE ISPSD 2024 under the name "Enhanced Gate Breakdown in β-Ga₂O₃ HJFET through a NiOx/GaOx p-n Junction Gate Stack." The first author is selected by Dr. Zhou.

Figure 5. Schematic diagram of (a) Gallium Oxide PN-HJFET device and (b) Gallium Oxide S/ohmic-HJFET device structures, (c) gate current-voltage (I_G-V_G) characteristics of PN-HJFET device, (d) gate current-voltage characteristics of PN-HJFET device measured at temperature range 25-250 ℃, (e) Arrhenius curve of I-_G1000 /T, (f) activation energy e extracted from Figure (E_A).

      5、Kilovolt nitrogen ion implanted Gallium Oxide vertical transistor

      Due to the challenging implementation of P-type Gallium Oxide, the realization of Gallium Oxide enhanced transistors has been limited to a certain extent. The acceptor doping can compensate the carrier in Gallium Oxide and realize the current barrier layer in Gallium Oxide material, which provides a new idea for the realization of enhanced mode FET. The main methods for forming current barrier layer in Gallium Oxide include high temperature annealing in oxygen atmosphere, magnesium doping and nitrogen doping. However, in the present study, the leakage characteristic of the current barrier layer is still not ideal, resulting in high leakage current in the off state of the device, which is easy to cause premature breakdown of the device. In this work, the current barrier layer is realized by nitrogen ion implantation, and the leakage of the current barrier layer is suppressed by optimizing the annealing activation temperature after ion implantation. Based on the optimized post-ion implantation annealing process, the work achieved a U-shaped slot gate vertical transistor with a breakdown voltage higher than 1 kV, which showed a significant increase in breakdown voltage compared with the pre-optimized device, initially demonstrating the potential of Gallium Oxide vertical transistors based on the current barrier layer, as shown in Figure 6. The research results were published in IEEE ISPSD 2024 under the title "1-KV-β-GAO₂ UM₃OSFET with Quasi-Inversion Nitrogen-Ion-Implanted Channel". And won the only Best Poster Award at the conference, see Figure 7. Doctoral student Qi Liu and postdoc Zhou Xuanze as the co-first authors of the paper.

Figure 6. (a) Schematic diagram of β-Ga2O3 UMOSFET device structure, (b) current-voltage characteristics of test structures without current barrier layer (CBL) and with CBL annealed at 1100℃ and 1150℃, respectively. (c) Pulse output characteristics of UMOS A (annealed at 1100℃) and (d) UMOS B (annealed at 1150℃) devices, and breakdown characteristics of (e) UMOS A (annealed at 1100℃) and (f) UMOS B (annealed at 1150℃) devices.

FIG. 7. The award ceremony of Liu Qi, PhD student of our university (Best Poster Award).

      The above five research achievements were supported by the National Natural Science Foundation of China, the Chinese Academy of Sciences, the Commission of Science and Technology, the Research and Development Plan of Guangdong Province in Key Fields, the Key Youth Innovation Project of USTC, and the Micro and Nano Research and Manufacturing Center and the Experimental Center of Information Science of USTC.