【Device Papers】High Voltage Design Strategies for Gallium Oxide Power Devices

      Researchers from the Swansea University have published a dissertation titled "High Voltage Design Strategies for Gallium Oxide Power Devices" in IEEE Transactions on Semiconductor Manufacturing.

Abstract

      This study employs drift-diffusion simulation to investigate key factors influencing the performance of β-Ga₂O₃ FinFETs, demonstrating that enhancement-mode behaviour (Vth 0) is achievable for β-Ga₂O₃ FinFET using a Fin width WFIN≤0.5 μm and doping concentration Nd≤1×101 cmtextsuperscript-. Breakdown voltage and output/transfer characteristics are calculated by using drift-diffusion methodology calibrated by experiments. We found that the metal work function (ms), dielectric constant (κ), and unintentional negative interface charge density (-Qf) at the β-Ga₂O₃/dielectric interface significantly impact Vth, with a high ms being necessary for enhancement mode (E-mode) operation. To achieve 5kV breakdown, a WFIN of 200 nm requires a fin thickness (TFIN) of 0.8 μm, a WFIN of 400 nm requires TFIN1.2 μm, and a WFIN 600 nm requires TFIN 2 μm. From WFIN of 200 nm to 400 nm, DIBL (drain induced barrier lowering, i.e. Vth /Vds) increases by 300%, while from 400 to 600 nm, it rises by only 100%. The presence of -Qf enhances the breakdown voltage by mitigating DIBL-related failure mechanisms and by redistributing the electric potential away from the gate dielectric and deeper into the β-Ga₂O₃ drift region. A controllable and relatively defect-free process was developed for Ga₂O₃ metal-insulator-semiconductor (MIS) structures, enabling improved interface quality. Capacitance–voltage measurements and progressive annealing studies demonstrate enhanced device stability and reduced hysteresis for the proposed FinFET application. Finally, an optimized β-Ga₂O₃ fin etch process was developed on the KLA SPTS SynapsEtchmodule for Ga₂O₃ technology integration.

DOI：

https://doi.org/10.1109/TSM.2025.3597872