【Device Papers】Design of an Enhanced Mode of Ga₂O₃ Vertical MOSFET with Innovative Al₂O₃/NiO/Ga₂O₃ Structure

      Researchers from the Chongqing University of Technology have published a dissertation titled "Design of an Enhanced Mode of Ga₂O₃ Vertical MOSFET with Innovative Al₂O₃/NiO/Ga₂O₃ Structure" in 2025 International Conference on Advanced Semiconductor Devices and Integration Technology (ASDIT).

Abstract

      This study investigates a Ga₂O₃ vertical MOSFET with an Al₂O₃/NiO/Ga₂O₃ gate stack structure. The results indicate that the NiO layer establishes a 1.5 electron-volt barrier height at the interface with Ga₂O₃, thereby contributing to improved device performance and enhanced operational characteristics. In addition, this study systematically analyzed the impact of the drain-induced barrier lowering (DIBL) effect on device characteristics. It identified critical design parameters for sustaining enhanced performance under high-voltage operating conditions: the mesa width (WM) was set to 0.1 μm and the mesa height (TM) to 2.0 μm. Subsequently, based on WM = 0.1 μm and TM = 2.0 μm, the correlation between drift layer thickness, breakdown voltage, and specific on-resistance was systematically analyzed. When the drift layer thickness was set to 16 μm, the figure of merit achieved its peak value of 7.75 GW/cm², with a corresponding breakdown voltage of 4.8 kV and an on-resistance of 3.07 mΩ·cm². This study facilitates the optimization of Ga₂O₃ vertical MOSFETs for enhanced-mode operation.

DOI：

https://doi.org/10.1109/ASDIT66826.2025.11290918