【Patenes】Gallium Oxide Patent Weekly Report (Issue 3, July): Focusing on Material Preparation, Defect Engineering, Power Devices, and Optoelectronic Applications

 Introduction

      To further strengthen information exchange within the gallium oxide industry and help stakeholders stay informed of the latest technological developments, the Asian Gallium Oxide Alliance (AGOA) has launched the Gallium Oxide Patent Weekly column. This series will continuously compile and publish newly disclosed patent applications and technological advances in the gallium oxide field.

      As an important indicator of technological innovation, patents reflect R&D trends and strategic layout across the industrial chain. This column focuses on crystal growth, material preparation, defect engineering, device development, process optimization, and emerging applications, providing enterprises, universities, and research institutes with insights into technology trends while supporting the continued development of the gallium oxide industry.

      This third issue reviews gallium oxide-related patent applications published during the third week of July 2026 (July 13 – July 19).

 

1.A Simulation Analysis Method for the Atomic Layer Deposition Process of β-Ga₂O₃Materials (Published on July 14)

      According to information from the China National Intellectual Property Administration (CNIPA), Harbin Institute of Technology has filed a patent application titled “A Simulation Analysis Method for the Atomic Layer Deposition Process of β-Ga₂O₃ Materials”, with the publication number CN122392662A and application number 2026106142047.

      The patent discloses a simulation analysis method, system, device, and medium for the atomic layer deposition (ALD) process of β-Ga₂O₃ materials, involving semiconductor material fabrication technologies. The method includes constructing a supercell model of β-Ga₂O₃, performing surface hydrogen passivation and structural relaxation optimization to obtain a growth substrate model, and defining precursor materials under a simulated reaction environment. Based on the simulated conditions and parameters, multiple reaction pathways during the ALD process are simulated to obtain stable intermediate structures corresponding to each pathway. By analyzing the energy data of these stable intermediates, the reaction barriers and activation energies of β-Ga₂O₃ during atomic layer deposition are determined.

      This invention addresses the difficulty of deeply understanding deposition mechanisms through conventional experimental methods and enables effective simulation-based analysis of atomic-scale deposition processes.

 

2.Gallium Oxide Heterojunction Diode Based on an Extended Junction Termination Extension Structure and Preparation Method Thereof (Published on July 14)

      According to the information from the China National Intellectual Property Administration (CNIPA), Xi’an University of Electronic Science and Technology has filed a patent application titled “Gallium Oxide Heterojunction Diode Based on an Extended Junction Termination Extension Structure and Preparation Method Thereof”, with publication number CN122395963A and application number 2026105400728.

      According to the patent abstract, the invention discloses a gallium oxide heterojunction diode based on an extended junction termination extension (JTE) structure and a fabrication method thereof. It mainly addresses the issues of electric field crowding at the edge of the junction termination extension structure and poor device stability in existing gallium oxide heterojunction diodes.

      The device consists of a Ti/Au metal layer, n⁺ β-Ga₂O₃ substrate, n-type β-Ga₂O₃ epitaxial layer, main junction layer, junction termination extension layer, terminal bevel extension layer, passivation layer, and Ni/Au metal layer. The junction termination extension layer is located beneath the main junction layer, while the terminal bevel extension layer is positioned on one side of the main junction layer and the junction termination extension layer. Together, these three components form a composite termination structure, which alleviates electric field concentration at the edge of the anode metal contact.

      The passivation layer is formed above the composite termination structure to further expand and optimize the internal electric field distribution. The bevel angles of both the junction termination extension layer and terminal bevel extension layer can be adjusted to optimize device performance.

      This invention reduces the peak electric field intensity, improves interface characteristics, and enhances electrical stability, providing a promising structure for high-performance gallium oxide power devices.

 

3.A Method for Room-Temperature Fabrication of Amorphous Gallium Oxide Optoelectronic Synaptic Devices and Applications Thereof (Published on July 14)

      According to information from the China National Intellectual Property Administration (CNIPA), Shandong First Medical University (Shandong Academy of Medical Sciences) has filed a patent application titled “A Method for Room-Temperature Fabrication of Amorphous Gallium Oxide Optoelectronic Synaptic Devices and Applications Thereof”, with publication number CN122396100A and application number 2026105104419.

      According to the patent abstract, the invention relates to a method for fabricating amorphous gallium oxide optoelectronic synaptic devices at room temperature and their applications, within the field of semiconductor devices.

      The method utilizes room-temperature sputtering to form an amorphous gallium oxide channel layer on a gate dielectric layer. By adjusting the power of magnetron sputtering, the oxygen vacancy concentration in the amorphous gallium oxide layer is precisely controlled, enabling the generation of persistent photoconductivity and synaptic response characteristics.

      Under 254 nm ultraviolet pulse illumination, the device produces postsynaptic currents, enabling applications in UV-induced skin damage sensing simulation and pain sensitization simulation. In addition, the device can convert acoustic data into cochleagrams and further transform them into postsynaptic current features for snore recognition.

      This approach combines room-temperature fabrication, low energy consumption, complete optoelectronic synaptic functionality, and information-processing capabilities for healthcare monitoring applications, providing a potential pathway for the development of intelligent sensing devices based on amorphous gallium oxide.

 

4.Flexible Fiber-Based Gallium Oxide Photodetector for Underwater Solar-Blind Optical Communication (Published on July 14)

      According to information from the China National Intellectual Property Administration (CNIPA), Shengzhou Innovation Institute Co., Ltd. of Zhejiang Sci-Tech University and Zhejiang Sci-Tech University have filed a patent application titled “Flexible Fiber-Based Gallium Oxide Photodetector for Underwater Solar-Blind Optical Communication”, with publication number CN122384973A and application number 2026104941806.

      According to the patent abstract, the invention discloses a flexible fiber-based gallium oxide photodetector for underwater solar-blind optical communication, belonging to the fields of optoelectronic detection and underwater optical communication. It addresses challenges associated with existing underwater photodetectors, including poor flexibility, failure under bending conditions, detection blind spots, limited operational stability, and weak anti-interference capability.

      The proposed photodetector uses flexible carbon fiber as the substrate, with gallium oxide nanorod arrays grown in situ to form the working electrode. The device demonstrates key advantages, including stable performance after 1,000 repeated bending cycles, 360° omnidirectional detection without blind spots, and continuous underwater operation for 1.5 hours without signal degradation.

      The fabrication process mainly includes carbon fiber cleaning, immersion in gallium nitrate solution, hydrothermal growth, annealing treatment, device assembly, and performance testing.

      By analyzing the current–time (I–t) signals collected by the device, matching light/dark current variations with digital signals, and decoding information through an ASCII code database, the proposed detector enables underwater solar-blind ultraviolet optical communication. The device provides a promising solution for flexible, stable, and interference-resistant optical communication systems in complex underwater environments.

 

5.A Method for Forming a Composite Gate Dielectric Structure for Gallium Oxide MOSFETs and Device Thereof (Published on July 14)

      According to information from the China National Intellectual Property Administration (CNIPA), Rongjia (Chengdu) Semiconductor Co., Ltd. has filed a patent application titled “A Method for Forming a Composite Gate Dielectric Structure for Gallium Oxide MOSFETs and Device Thereof”, with publication number CN122395995A and application number 2026104811412.

      According to the patent abstract, the invention relates to semiconductor device technology, specifically a method for forming a composite gate dielectric structure for gallium oxide MOSFETs and the corresponding device.

      The technical process includes providing a semiconductor substrate structure with a gallium oxide channel layer, followed by ion implantation on the gallium oxide substrate to form the source region, drain region, and functional regions. After ion implantation, a first ultra-thin interface modulation layer is formed on the surface of the gallium oxide channel layer, followed by high-temperature annealing treatment.

      After the annealing process, a second main gate dielectric layer is deposited on the first interface modulation layer. The first ultra-thin interface modulation layer and the second main gate dielectric layer together form a composite gate dielectric structure. A gate electrode is then fabricated on the second gate dielectric layer to complete the gallium oxide channel MOSFET.

      This invention enables compatible integration of high-temperature activation processes with high-quality gate dielectric formation, significantly improving the interface quality and device reliability of gallium oxide MOSFETs, providing a potential approach for enhancing the performance and stability of next-generation gallium oxide power devices.

 

6.A Gallium Oxide p–n Junction, Fabrication Method, and Applications Thereof (Published on July 14)

      According to information from the China National Intellectual Property Administration (CNIPA), The Hong Kong University of Science and Technology (Guangzhou) has filed a patent application titled “A Gallium Oxide p–n Junction, Fabrication Method, and Applications Thereof”, with publication number CN122396219A and application number 2026104772776.

      According to the patent abstract, the invention provides a gallium oxide p–n junction, its fabrication method, and applications thereof.

      The fabrication method includes in-situ growth of n-type β-Ga₂O₃ layers and/or p-type β-Ga₂O₃ layers on n-type or p-type β-Ga₂O₃ substrates, followed by electrode fabrication to obtain the gallium oxide p–n junction device.

      During the preparation of p-type β-Ga₂O₃ substrates and p-type β-Ga₂O₃ layers, Te and Mg sources are used as p-type dopants. When the total number of n-type and p-type β-Ga₂O₃ epitaxial layers is no less than two, the growth of n-type and p-type β-Ga₂O₃ layers is controlled within the same MOCVD reactor chamber.

      The proposed method enables the fabrication of high-quality gallium oxide p–n junctions with low interface defect density, resulting in devices with excellent rectification characteristics, high breakdown voltage, and outstanding operational stability. This work provides a potential pathway for advancing gallium oxide-based bipolar devices and high-performance power semiconductor applications.

 

7.A Gallium Oxide Power Transistor with a High-Resistance Gallium Oxide Thin Layer and Fabrication Method Thereof (Published on July 14)

      According to information from the China National Intellectual Property Administration (CNIPA), Xidian University has filed a patent application titled “A Gallium Oxide Power Transistor with a High-Resistance Gallium Oxide Thin Layer and Fabrication Method Thereof”, with publication number CN122395994A and application number 2026104712864.

      According to the patent abstract, the invention discloses a gallium oxide power transistor containing a high-resistance gallium oxide thin layer and its fabrication method, belonging to the field of gallium oxide transistor technologies.

      The device structure consists of, from bottom to top, a substrate, buffer layer, conductive channel layer, high-resistance gallium oxide thin layer, gate dielectric layer, and gate electrode. The source and drain electrodes are connected on both sides of the gate electrode and electrically connected with the conductive channel layer. The resistivity of the high-resistance gallium oxide thin layer is higher than that of the conductive channel layer.

      The proposed structure effectively suppresses electron leakage from the channel layer toward the gate electrode, thereby directly reducing gate leakage current. It improves the dielectric reliability of the gate structure and enhances the long-term operational stability of gallium oxide power transistors, providing a promising approach for improving the reliability of next-generation gallium oxide power devices.

 

8.A High-Voltage Gallium Oxide Reverse-Blocking Device and Fabrication Method Thereof (Published on July 14)

      According to information from the China National Intellectual Property Administration (CNIPA), Xidian University has filed a patent application titled “A High-Voltage Gallium Oxide Reverse-Blocking Device and Fabrication Method Thereof”, with publication number CN122395980A and application number 2026104644960.

      According to the patent abstract, the invention discloses a high-voltage gallium oxide reverse-blocking device and its fabrication method, belonging to the field of gallium oxide power semiconductor devices.

      The device includes a Ga₂O₃ substrate layer, a Ga₂O₃ epitaxial layer located on the substrate, an n⁺ heavily doped ion-implanted region formed in the source region of the epitaxial layer, and a source electrode positioned on and in contact with the n⁺ implanted region, forming an ohmic contact.

      A drain electrode is formed in the drain region of the Ga₂O₃ epitaxial layer, where the drain electrode may form a Schottky contact with the Ga₂O₃ epitaxial layer. Alternatively, the drain electrode may be formed on a p-type oxide layer located on the Ga₂O₃ epitaxial layer, forming an ohmic contact with the p-type oxide layer.

      A gate electrode is positioned between the source and drain regions on the Ga₂O₃ epitaxial layer, forming a Schottky contact with the epitaxial layer.

      The proposed structure enables high-voltage reverse-blocking capability by optimizing the device architecture and contact design, providing a potential solution for improving the breakdown performance and reliability of gallium oxide power semiconductor devices.

 

9.A Simulation Analysis Method for the Atomic Layer Deposition Process of β-Gallium Oxide Materials (Published on July 14)

      According to information from the China National Intellectual Property Administration (CNIPA), Xidian University has filed a patent application titled “A  Simulation Analysis Method for the Atomic Layer Deposition Process of β-Gallium Oxide Materials”, with publication number CN122395968A and application number 2026104632253.

      According to the patent abstract, the invention discloses a gallium oxide diode containing a highly doped buried layer and its fabrication method, belonging to the field of ultra-wide-bandgap semiconductor technologies.

      The gallium oxide diode comprises, from bottom to top, a cathode, a heavily doped n⁺-type gallium oxide substrate, a gallium oxide epitaxial drift region, and a Schottky anode. A locally highly doped buried layer is embedded inside the gallium oxide epitaxial drift region and is positioned directly beneath the Schottky anode.

      A buffer spacing with a predetermined thickness is designed between the upper surface of the highly doped buried layer and the Schottky anode. The corresponding region within the buffer spacing maintains the same low doping concentration as the main body of the gallium oxide epitaxial drift region.

      The doping concentration of the locally highly doped buried layer is higher than the background doping concentration of the gallium oxide epitaxial drift region but lower than that of the heavily doped n⁺-type gallium oxide substrate.

      The proposed diode structure achieves a balance between high breakdown voltage and low on-resistance, offering a promising approach for improving the performance of high-power gallium oxide semiconductor devices.

 

10.A Vertical Reverse-Conducting Gallium Oxide Field-Effect Transistor with a P-Type Control Region(Published on July 14)

      According to the information released by the China National Intellectual Property Administration (CNIPA), the University of Electronic Science and Technology of China has filed a patent application titled “A Vertical Reverse-Conducting Gallium Oxide Field-Effect Transistor with a P-Type Control Region” (Publication No.: CN122396003A, Application No.: 2026104511668), which was published on July 14.

      The patent discloses a vertical reverse-conducting gallium oxide field-effect transistor with a P-type control region, belonging to the field of power semiconductor technology.

      The invention introduces a P-type control region into the device structure. Under zero bias, the gate metal and the P-type control region jointly deplete the fin-shaped conductive channel, enabling a normally-off operation mode and increasing the threshold voltage.

      During forward blocking, the depletion region formed between the P-type control region and the gallium oxide drift layer expands and overlaps, effectively shielding the high electric field at the corners of the fin channel and the edge of the freewheeling diode metal, thereby improving the breakdown voltage.

      During forward conduction, an electron accumulation layer forms along the sidewalls of the fin-shaped channel. Meanwhile, the depletion effect of the P-type control region allows the use of higher doping concentrations, enhancing current capability and reducing on-resistance.

      During reverse freewheeling operation, the diode region forms a low-barrier metal-semiconductor contact with gallium oxide. As the reverse bias increases, the PN junction in the diode region provides an additional conduction path, further reducing on-resistance and improving current handling capability.

 

11.An Indium Gallium Zinc Oxide Thin-Film Transistor, Preparation Method, and Application(Published on July 14)

      According to the information released by the China National Intellectual Property Administration (CNIPA), South China University of Technology has filed a patent application titled “An Indium Gallium Zinc Oxide Thin-Film Transistor, Preparation Method, and Application” (Publication No.: CN122396015A, Application No.: 2026104084102), which was published on July 14.

      The patent discloses an indium gallium zinc oxide (IGZO) thin-film transistor (TFT), its preparation method, and applications.

      The IGZO thin-film transistor comprises a substrate, active layer, gate insulating layer, gate electrode, dielectric layer, passivation layer, source electrode, and drain electrode. The active layer includes at least one zinc oxide–indium oxide–gallium oxide (ZnO–In₂O₃–Ga₂O₃) composite layered structure, consisting of stacked zinc oxide, indium oxide, and gallium oxide layers.

      The dielectric layer completely covers the active layer, gate insulating layer, and gate electrode, while the source and drain electrodes extend through the dielectric layer and establish electrical contact with the substrate.

      The proposed IGZO thin-film transistor features high carrier mobility, excellent positive bias temperature stress (PBTS) stability, and improved negative bias illumination temperature stress (NBITS) stability. It is well suited for high-resolution and high-refresh-rate display panels and demonstrates strong potential for large-scale industrial manufacturing and applications.

 

12.A Gallium Oxide Device with a Gradient Gate Dielectric Structure and Fabrication Method Thereof(Published on July 14)

      According to information released by the China National Intellectual Property Administration (CNIPA), Sun Yat-sen University has filed a patent application titled “A Gallium Oxide Device with a Gradient Gate Dielectric Structure and Fabrication Method Thereof” (Publication No.: CN122396025A, Application No.: 2026103313797), which was published on July 14.

      The patent discloses a gallium oxide device featuring a gradient gate dielectric structure and its fabrication method, targeting the performance limitations of short-channel devices.

      The device incorporates a gradient dielectric layer and a gradient gate electrode layer on the gallium oxide epitaxial layer. The gradient dielectric layer is designed to regulate the electric field distribution beneath the gate and enhance gate-channel coupling. Its dielectric constant exhibits a stepwise gradient variation, increasing from the source side toward the drain side.

      The gradient gate electrode layer is used to regulate the surface potential distribution of the channel, with its work function gradually decreasing from the source side toward the drain side.

      This structure enables synergistic control of channel potential distribution and gate electric field distribution, effectively reducing the modulation effect of drain voltage on the channel barrier, suppressing channel length modulation and output conductance, and improving current saturation characteristics.

      Meanwhile, the gradient structure reduces the peak electric field at the gate-drain edge and mitigates electric field crowding, making it particularly suitable for short-channel gallium oxide devices.

 

13.HVPE System and Method for Growing β-Ga₂O₃Thin Films(Published on July 17)

      According to CNIPA information, Suzhou Liaoyuan Semiconductor Co., Ltd. has filed a patent application titled “System and Method for Growing β-Ga₂O₃ Thin Films Using HVPE” (Publication No.: CN122406183A; Application No.: 2026106933880).

      The patent discloses an HVPE growth system for β-Ga₂O₃ thin films, featuring a six-zone horizontal tube furnace. The system includes a substrate holder, gas buffer components, quartz tubes, three gas inlet channels, gallium boat, and exhaust outlet.

      The gallium boat is placed in the second temperature zone, while the substrate holder is positioned in the fifth temperature zone. Hydrogen chloride, oxygen, and nitrogen gases are introduced through three independent gas channels. The substrate holder adopts a hollow structure with the substrate placed upside down and the growth surface facing downward, allowing oxide particles generated from gas-phase pre-reactions to naturally fall away under gravity. A gas buffer component installed in the fourth temperature zone suppresses unwanted gas-phase reactions.

      By optimizing temperature, gas flow rate, and growth time, the method enables stable growth of high-quality β-Ga₂O₃ thin films. The technology reduces dislocations and polycrystalline defects, improves crystallinity and uniformity, supports various substrate sizes, increases single-furnace production capacity, and offers potential for industrial-scale β-Ga₂O₃ thin-film manufacturing.

 

      In addition to patents focusing on gallium oxide materials, several patents published this week also involve the application of gallium oxide as a functional material in other fields, which are provided for readers’ reference.

 

1.IZO Ceramic Target Material, Preparation Method, and Applications(Published on July 14)

      According to information from the China National Intellectual Property Administration (CNIPA), Fujian Acetron New Materials Co., Ltd. has filed a patent application titled “IZO Ceramic Target Material, Preparation Method Thereof, and Applications” (Publication No.: CN122380806A; Application No.: 2026106060121).

      The patent discloses an IZO ceramic target material and its preparation method and applications. The IZO ceramic target consists of a base oxide and doped metal oxides. The base oxide includes indium oxide (In₂O₃) and zinc oxide (ZnO), while the doped metal oxides include titanium oxide, zirconium oxide, hafnium oxide, tin oxide, or gallium oxide. The mass ratio between the base oxides and doped metal oxides ranges from (93–108):(0.01–1.0).

      By introducing doped metal oxides into the IZO matrix, the invention enhances the amorphous network structure at the microscopic level and precisely regulates carrier behavior, thereby widening the optical bandgap and reducing intrinsic optical absorption. Meanwhile, controlling the amount of dopant addition enables trace dopant ions to effectively passivate bulk and interface defects, improve material densification, reduce surface and bulk scattering, and further enhance visible-light transmittance.

      This technology provides a pathway for developing high-performance IZO transparent conductive materials with improved optical and electrical properties.

 

2.Inverted Perovskite Solar Cell and Preparation Method Thereof(Published on July 14)

      According to information from the China National Intellectual Property Administration (CNIPA), Renshuo Photonics (Suzhou) Co., Ltd., Renshuo Photonics (Changshu) Co., Ltd., and Jiangsu Renshuo Photovoltaic Technology Co., Ltd. have jointly filed a patent application titled “Inverted Perovskite Solar Cell and Preparation Method Thereof” (Publication No.: CN122396143A; Application No.: 2026105150493).

      The patent discloses an inverted perovskite solar cell and its preparation method. The device comprises a stacked structure consisting of a transparent bottom electrode layer, hole transport layer, perovskite absorber layer, electron transport layer, buffer layer, barrier layer, and back electrode layer.

      The electron transport layer is composed of a fullerene layer or fullerene derivative layer, while the buffer layer is a transparent conductive oxide layer. The barrier layer is formed by an aluminum-doped gallium oxide (Al-doped Ga₂O₃) layer, with an aluminum atomic content ranging from 3% to 10%. The back electrode layer includes a transparent top electrode layer positioned above the Al-doped Ga₂O₃ barrier layer.

      By introducing an Al-doped Ga₂O₃ layer between the fullerene-based electron transport layer, transparent conductive oxide layer, and transparent top electrode layer, the invention significantly improves both the efficiency and stability of the device. It also enables the use of thicker barrier layers, reducing the difficulty of controlling thin-film formation processes and enhancing the industrial feasibility of the proposed technology.

 

3.Micron-Scale Gallium Oxide Powder, Preparation Method and Application Thereof(Published on July 14)

      According to information from the China National Intellectual Property Administration (CNIPA), the National University of Defense Technology has filed a patent application titled “Micron-Scale Gallium Oxide Powder, Preparation Method and Application Thereof”, with publication number CN122380432A and application number 202510050147X.

      The patent discloses a micron-scale gallium oxide powder, its preparation method, and applications. The preparation process includes mixing gallium salts with water to form a gallium ion solution, adjusting the pH value of the solution to ≤6 under stirring conditions, conducting a hydrothermal reaction to obtain a gallium oxide precursor, and finally obtaining micron-scale gallium oxide powder through calcination.

      The prepared micron-scale gallium oxide powder exhibits excellent broadband reflection performance and stability. Its solar reflectance reaches 93.4%, while the average reflectance in the mid-infrared wavelength range reaches 68.4%, significantly enhancing outdoor cooling performance. In addition, the powder effectively reflects ultraviolet radiation, further improving cooling efficiency.

      The material maintains excellent physical and chemical stability under harsh environments such as high temperatures, ultraviolet exposure, and acidic or alkaline conditions. It can be widely used as a filler for various thermal insulation coatings, offering long service life and superior adaptability in extreme climatic environments.

 

4.Semiconductor Device and Method for Manufacturing the Semiconductor Device Thereof(Published on July 17)

      According to information from the China National Intellectual Property Administration (CNIPA), Semiconductor Energy Laboratory Co., Ltd. has filed a patent application titled “Semiconductor Device and Method for Manufacturing the Semiconductor Device Thereof”, with publication number CN122423323A and application number 202480081348X.

      The patent discloses a semiconductor device designed to achieve high on-state current. The device includes a first conductive layer, a first insulating layer formed on the first conductive layer, a second conductive layer formed on the first insulating layer, an oxide layer, a first oxide semiconductor layer formed on the oxide layer, a second oxide semiconductor layer formed on the first oxide semiconductor layer, a second insulating layer formed on the second oxide semiconductor layer, and a third conductive layer formed on the second insulating layer.

      The first conductive layer includes a first recessed portion. The first insulating layer and the second conductive layer are provided with a first opening at a position overlapping the recessed portion. The first oxide semiconductor layer faces the first insulating layer through the oxide layer within the first opening. The third conductive layer faces the first oxide semiconductor layer through the second insulating layer within the first opening.

      The oxide layer contains gallium oxide (Ga₂O₃), while the first oxide semiconductor layer contains indium oxide (In₂O₃), and the second oxide semiconductor layer contains gallium and/or indium.

      This structure enables improved semiconductor device performance with enhanced on-state current capability, providing potential for high-performance oxide semiconductor applications.