【Member Papers】NH₃ Plasma Surface Treatment in β-Ga₂O₃: Interface Trap Density Reduction and MOSFET Performance Gains

Background

      β-phase gallium oxide (β-Ga₂O₃) is an emerging ultra-wide bandgap semiconductor with the potential for low-cost substrate preparation, making it a core candidate material for next-generation power devices. Over the past decade, remarkable progress has been made in the research and development of β-Ga₂O₃ MOSFETs. However, the defects at the dielectric/semiconductor interface have always been the key bottleneck limiting device performance and reliability, leading to threshold voltage shift, large hysteresis, degraded subthreshold swing and other issues. Al₂O₃ has become the mainstream gate dielectric for β-Ga₂O₃ MOSFETs due to its large conduction band offset, moderate permittivity and excellent compatibility with atomic layer deposition. Traditional interface treatment methods such as wet chemical cleaning and post-deposition annealing can only reduce the interface trap density to the order of 10¹² eV⁻¹·cm⁻², which cannot meet the requirements of high-performance devices. Ammonia plasma treatment (NPT) has been verified to have interface passivation effects in Si, GaAs and GaN systems, and the team has previously applied it to β-Ga₂O₃ Schottky barrier diodes and achieved reduced interface states. However, the systematic research of this process in the interface engineering of β-Ga₂O₃ MOSFETs is still blank.

Abstract

      In this work, an NH₃ plasma treatment (NPT) is introduced to engineer the Al₂O₃ / β-phase gallium oxide (β-Ga₂O₃) interface for high-performance MOS devices. The NPT effectively suppresses Ga suboxide-related surface states, leading to substantial reduction of interface trap density (D_it). High–low frequency capacitance analysis of Al₂O₃ / β-Ga₂O₃ MOS capacitors (MOSCAPs) reveals a record-low shallow-level D_it of 2 ×10¹⁰ cm⁻² eV⁻¹. X-ray photoelectron spectroscopy (XPS) confirms a 31% reduction in Ga⁺ suboxide components after NPT, indicating improved surface stoichiometry. The improved interface quality directly translates into enhanced transistor performance. β-Ga₂O₃ metal–oxide–semiconductor field-effect transistors (MOSFETs) with NPT exhibit reduced subthreshold swing (SS), suppressed hysteresis, ∼10% enhancement in effective mobility, lower ON-resistance (R_ON), and increased breakdown voltage (V_br). These improvements are attributed to reduced Coulomb scattering and suppressed charge trapping at the dielectric/semiconductor interface. The demonstrated NPT process is fully CMOS-compatible and integration-friendly, offering a practical and scalable interface engineering strategy for realizing high-performance and reliable β-Ga₂O₃ power transistors.

Highlights

      NH₃plasma treatment (NPT) is systematically applied to Al₂O₃/β-Ga₂O₃ interface engineering for the first time, achieving a record-low interface trap density of 2×10¹⁰ cm⁻²·eV⁻¹;

      XPS confirms that NPT reduces the Ga⁺suboxide component on β-Ga₂O₃ surface by 31%, revealing the interface passivation mechanism at the chemical level;

      NPT process simultaneously improves multiple core performances of β-Ga₂O₃MOSFETs: 12.6% reduction in subthreshold swing, 46.5% reduction in hysteresis, ~10% enhancement in effective mobility, lower ON-resistance and higher breakdown voltage;

      The process is fully CMOS-compatible with no vacuum break and negligible ion bombardment damage, featuring industrial scalability.

Conclusion

      In conclusion, an NPT has been systematically implemented to engineer the β-Ga₂O₃ surface prior to Al₂O₃ deposition, effectively mitigating Ga suboxide-related defects and significantly improving the dielectric/semiconductor interface quality. The Al₂O₃ / β-Ga₂O₃ MOSCAPs exhibit an ultralow shallow-level D_it of 2 ×10¹⁰ cm⁻² eV⁻¹, representing a record-low value for this material system. β-Ga₂O₃ MOSFETs incorporating NPT demonstrate reduced SS, suppressed hysteresis, lower R_ON, and improved V_br, collectively indicating strengthened electrostatic control, reduced Coulomb scattering, and enhanced dielectric robustness. As a result, as a CMOS-compatible and integration-friendly surface engineering strategy, NPT provides an effective and scalable pathway toward high-performance and reliable β-Ga₂O₃ power transistors.

Project Support

      This work was supported in part by the National Key Research and Development Program of China under Grant 2024YFF1504400; in part by the National Natural Science Foundation of China under Grant 62293522, Grant 62204255, Grant 62234007, Grant 62025402, Grant 92564302, Grant 92564303, Grant 92364204, Grant 92264202, Grant 92464205, and Grant U23A20351; in part by the Key Program of Shaanxi Provincial Department of Science and Technology under Grant 2024CY2-GJHX-81; in part by the Key Program of Hangzhou City Department of Science and Technology under Grant 2025SZD1A26; in part by the Zhejiang Provincial Natural Science Foundation of China under Grant LDT23F0402 and Grant LDT23F04024F04; in part by Leading Innovation and Entrepreneurship Project of Zhejiang Province under Grant 2023R01014; and in part by Hangzhou Leading Talent Program.