【Patenes】Gallium Oxide Patent Weekly Report (Issue 12, September)

      To further strengthen information exchange within the gallium oxide industry and help stakeholders stay informed of the latest technological developments, the Asian Gallium Oxide Alliance (AGOA) has launched the Gallium Oxide Patent Weekly column. This series will continuously compile and publish newly disclosed patent applications and technological advances in the gallium oxide field.

      As an important indicator of technological innovation, patents reflect R&D trends and strategic layout across the industrial chain. This column focuses on crystal growth, material preparation, defect engineering, device development, process optimization, and emerging applications, providing enterprises, universities, and research institutes with insights into technology trends while supporting the continued development of the gallium oxide industry.

      This twelfth issue reviews gallium oxide-related patent applications published during the third week of September 2026 (September 14–September 20).

Method for Eliminating Stress in Ga₂O₃ Crystals and Applications (Published September 15)

      According to information from the China National Intellectual Property Administration (CNIPA), Hangzhou Garen Semiconductor Co., Ltd. has filed a patent application entitled “A Method for Eliminating Stress in Ga₂O₃ Crystals and Applications.” The publication number is CN122751360A, and the application number is 202611174694X.

      The invention relates to the field of semiconductor materials, and specifically discloses a method for eliminating stress in Ga₂O₃ crystals and applications thereof.

      The method comprises the following steps:(a) subjecting a Ga₂O₃ crystal to surface roughening treatment and surface oxide coating treatment; and(b) annealing the Ga₂O₃ crystal after the surface oxide coating treatment in an oxygen-containing atmosphere.

      The method enables high-temperature annealing in a high-oxygen atmosphere to be carried out independently, thereby thoroughly eliminating residual stress inside the crystal. By separating the annealing process from the crystal-growth furnace, the method can shorten the furnace occupancy cycle and avoid additional consumption of iridium components during annealing, allowing sufficient annealing time and optimized thermal-field conditions to be maintained without being constrained by furnace utilization costs.

      By eliminating internal stress before mechanical processing of the crystal, the method addresses the root causes of cracking during subsequent processing and helps ensure that the resulting substrate wafers achieve excellent surface flatness and wafer-shape uniformity.

Gate-All-Around Ga₂O₃ Field-Effect Transistor Based on Heterogeneous Integration and Method for Fabricating the Same (Published September 15)

      According to information from the China National Intellectual Property Administration (CNIPA), Xidian University has filed a patent application entitled “Gate-All-Around Ga₂O₃ Field-Effect Transistor Based on Heterogeneous Integration and Method for Fabricating the Same.” The publication number is CN122766018A, and the application number is 2026108262683.

      The invention relates to the fields of ultra-wide-bandgap semiconductor devices and micro/nanofabrication technology, and specifically discloses a gate-all-around (GAA) Ga₂O₃ field-effect transistor based on heterogeneous integration and a method for fabricating the same.

      The fabrication method for the heterogeneously integrated GAA Ga₂O₃ field-effect transistor comprises a heterogeneous substrate; an intermediate aluminum oxide (Al₂O₃) layer disposed on the heterogeneous substrate; and a Ga₂O₃ active layer disposed on the intermediate Al₂O₃ layer. The Ga₂O₃ active layer is patterned into a source region, a drain region, and multiple spaced Fin-type channel regions extending laterally between the source and drain regions.

      A gate dielectric layer is formed around the outer periphery of the Fin-type channel regions, covering their top surface, four sidewalls, and bottom surface. A gate metal layer is then formed outside the gate dielectric layer and arranged around the Fin-type channel regions correspondingly, thereby forming a gate-all-around structure. The source and drain electrodes are electrically connected to the respective source and drain regions.

Composite Ceramic Continuous-Feeding Apparatus for Ga₂O₃ Single-Crystal Growth (Published September 18)

      According to information from the China National Intellectual Property Administration (CNIPA), Unigrace New Energy Co., Ltd. has filed a patent application entitled “A Composite Ceramic Continuous-Feeding Apparatus for Ga₂O₃ Single-Crystal Growth.” The publication number is CN122773474A, and the application number is 2026110122084.

      The invention discloses an apparatus for continuous feeding and Czochralski growth of Ga₂O₃ single crystals, relating to the field of Ga₂O₃ single-crystal Czochralski growth equipment. The apparatus incorporates a composite ceramic gradient crucible within the main growth chamber, consisting of a corrosion-resistant inner layer, a thermal-buffer middle layer, and a conductive heating outer layer. Two sets of induction coils are arranged around the conductive heating outer layer and generate heat through non-contact electromagnetic coupling.

      A continuous-feeding auxiliary chamber supplies material through a central baffle to a telescopic feed tube after the internal atmosphere is balanced. During feeding, the telescopic tube extends into the main growth chamber toward the peripheral region near the inner edge of the crucible without penetrating the crucible. Once feeding is complete, the tube can be fully retracted from the furnace, and the opening in the furnace sidewall can be sealed with a sidewall cover.

      The apparatus helps maintain the sealing, thermal insulation, and atmospheric balance of the main growth chamber after crystal withdrawal, while reducing heat loss from the furnace after feeding is completed. These features provide favorable conditions for continued Czochralski growth of Ga₂O₃ single crystals, enabling successive crystal growth without requiring the main growth chamber to be opened.

New Diamond Superjunction Field-Effect Transistor Power Device (Published September 18)

      According to information from the China National Intellectual Property Administration (CNIPA), University of Electronic Science and Technology of China (UESTC) has filed a patent application entitled “A New Diamond Superjunction Field-Effect Transistor Power Device.” The publication number is CN122784137A, and the application number is 202610961108X.

      The invention belongs to the field of semiconductor technology and specifically provides a new diamond superjunction field-effect transistor power device. Based on a lateral diamond power device, the invention introduces an N-type doped gallium oxide (Ga₂O₃) region or an N-type doped aluminum nitride (AlN) region. This structure significantly increases the controllable doping concentration in the channel region while maintaining the same drift-region length.

      As a result, the device can substantially increase the blocking voltage of the lateral field-effect power transistor while effectively reducing its specific on-resistance, thereby improving overall device performance.

      In summary, all of the proposed new structural diamond field-effect transistor power devices exhibit characteristics of high voltage blocking capability and low specific on-resistance. Furthermore, the structures can effectively enhance the voltage-blocking capability of lateral field-effect power transistors even at higher drift-region doping concentrations.

      In addition to patents focusing on gallium oxide materials, several patents published this week also involve the application of gallium oxide as a functional material in other fields, which are provided for readers’ reference.

Thermal-Shock-Resistant Glass for Low-Earth-Orbit Spacecraft and Methods for Preparation and Applications (Published September 18)

      According to information from the China National Intellectual Property Administration (CNIPA), Qinhuangdao Xingjian Special Glass Co., Ltd. has filed a patent application entitled “Thermal-Shock-Resistant Glass for Low-Earth-Orbit Spacecraft and Methods for Preparation and Applications.” The publication number is CN122771614A, and the application number is 2026112314939.

      The invention relates to the field of glass technology and discloses thermal-shock-resistant glass for low-Earth-orbit (LEO) spacecraft, together with methods for its preparation and applications.

      The glass comprises the following raw materials, in parts by weight: silica sand, ammonium dihydrogen phosphate, boric acid, carbonates, zinc oxide, cerium dioxide, gallium oxide, indium oxide, vanadium pentoxide, lead oxide, antimony trioxide, sodium nitrate, tetrabutyl titanate, and kerosene. The mass ratio of the combined amount of zinc oxide and boric acid to the amount of silica sand is 1:1.45–1.55.

      According to the invention, the proposed formulation and preparation process address the insufficient resistance to thermal shock in the space environment of glass with a thickness greater than 30 mm for LEO spacecraft applications.