Patents
【Patenes】Gallium Oxide Patent Weekly Report (Issue 13, September)
日期：2026-10-10阅读：241
To further strengthen information exchange within the gallium oxide industry and help stakeholders stay informed of the latest technological developments, the Asian Gallium Oxide Alliance (AGOA) has launched the Gallium Oxide Patent Weekly column. This series will continuously compile and publish newly disclosed patent applications and technological advances in the gallium oxide field.
As an important indicator of technological innovation, patents reflect R&D trends and strategic layout across the industrial chain. This column focuses on crystal growth, material preparation, defect engineering, device development, process optimization, and emerging applications, providing enterprises, universities, and research institutes with insights into technology trends while supporting the continued development of the gallium oxide industry.
This thirteen issue reviews gallium oxide-related patent applications published during the fourth week of September 2026 (September 21–September 30).
A Composite Crucible for Gallium Oxide Crystal Growth and Preparation Method (Published September 22)
According to information released by the China National Intellectual Property Administration (CNIPA), Shandong SINOGa Valley Semiconductor Co., Ltd. has filed a patent application titled “A Composite Crucible for Gallium Oxide Crystal Growth and Preparation Method Thereof.” The publication number is CN122791473A, and the application number is 2026112053182.
The application discloses a composite crucible for gallium oxide crystal growth and a method for preparing the same, relating to the technical field of crucibles.
The composite crucible comprises a crucible substrate, with a transition layer and a functional layer sequentially deposited on its inner surface. On the outer surface, a transition layer, a functional layer, and an oxidation-resistant layer are sequentially arranged. The iridium content in the transition layer gradually increases with increasing distance from the crucible substrate. In addition, the composite crucible features a variable wall thickness along its height.
The proposed composite crucible reduces iridium consumption while improving crucible stability and service life, thereby helping ensure the quality of crystal growth.
Method for Producing a β-Ga₂O₃/β-Ga₂O₃ Laminate, a Laminate Obtained by the Method, and a Semiconductor Device Comprising the Laminate (Published September 22)
According to information released by the China National Intellectual Property Administration (CNIPA), Mitsubishi Gas Chemical Company, Inc. has filed a patent application titled “Method for Producing a β-Ga₂O₃/β-Ga₂O₃ Laminate, a Laminate Obtained by the Method, and a Semiconductor Device Comprising the Laminate.” The publication number is CN122804078A, and the application number is 2025800150912.
According to the invention, a method is provided for producing a β-Ga₂O₃/β-Ga₂O₃ laminate comprising a β-Ga₂O₃ substrate and a layer containing β-Ga₂O₃ single crystals formed on the substrate.
The method comprises forming the β-Ga₂O₃ single-crystal-containing layer on the β-Ga₂O₃ substrate by liquid-phase epitaxy using a gallium oxide melt containing a tetravalent foreign element and a divalent foreign element.
In the resulting β-Ga₂O₃ single-crystal-containing layer, the concentration difference between the tetravalent and divalent foreign elements ranges from −1 × 10¹⁹ to +1 × 10¹⁹ atoms/cm³, while the total content of foreign elements in the layer is less than 0.01 mol%.
A Gallium Oxide/Magnesium Nickel Oxide Heterojunction Photodetector and Preparation Method (Published September 25)
According to information released by the China National Intellectual Property Administration (CNIPA), Nanjing University of Posts and Telecommunications has filed a patent application titled “A Gallium Oxide/Magnesium Nickel Oxide Heterojunction Photodetector and Preparation Method.” The publication number is CN122825536A, and the application number is 2026112205522.
The invention discloses a gallium oxide/magnesium nickel oxide heterojunction photodetector comprising an alumina substrate, a gallium oxide epitaxial layer deposited on the alumina substrate, a magnesium nickel oxide thin-film layer deposited on the gallium oxide epitaxial layer, a first electrode forming an ohmic contact with the gallium oxide epitaxial layer, and a second electrode forming an ohmic contact with the magnesium nickel oxide thin-film layer.
The invention also discloses a preparation method for the gallium oxide/magnesium nickel oxide heterojunction photodetector. The gallium oxide epitaxial layer is fabricated by metal-organic chemical vapor deposition (MOCVD), while the magnesium nickel oxide thin-film layer is fabricated using magnetron sputtering.
The disclosed photodetector features a simple fabrication process and supports both self-powered photoresponse at zero-bias voltage and photoconductive response under applied bias. It is suitable for high-sensitivity, low-power solar-blind ultraviolet photodetection applications.
A Gallium Oxide Lateral Power Transistor with a Three-Dimensional Thermoelectric Collaborative Heat-Dissipation and Stepped Field-Plate Structure (Published September 25)
According to information from the China National Intellectual Property Administration (CNIPA), Xidian University has filed a patent entitled “A Gallium Oxide Lateral Power Transistor with a Three-Dimensional Thermoelectric Collaborative Heat-Dissipation and Stepped Field-Plate Structure,” with publication number CN122825472A and application number 2026111480791.
The present invention discloses a gallium oxide lateral power transistor with a three-dimensional thermoelectric collaborative heat-dissipation and stepped field-plate structure, belonging to the technical field of gallium oxide transistor devices, and intended to solve the technical problems of forward heat-dissipation bottlenecks and vertical dielectric breakdown risks in existing gallium oxide ultrahigh-voltage power devices. The gallium oxide lateral power transistor of the present invention comprises a substrate; an epitaxial channel layer is provided on the substrate; a source, a gate, and a drain are arranged at intervals in the lateral direction on the epitaxial channel layer; an aluminum oxide film continuously covers the epitaxial channel layer; the gate is disposed on the aluminum oxide film; and an aluminum nitride dielectric layer covers the aluminum oxide film and the gate. The source is electrically connected to a first source field plate; the first source field plate extends laterally from the source and covers directly above the gate, and conformally adheres to the stepped morphology, forming a first stepped raised structure and being laid above the drift region as a bottom in-plane heat collection layer.
A UV Photodetector and Preparation Method (Published September 25)
According to information released by the China National Intellectual Property Administration (CNIPA), Beijing Electronics Holding Integrated Circuit Manufacturing Co., Ltd. has filed a patent application titled “A UV Photodetector and Preparation Method.” The publication number is CN122825533A, and the application number is 2026111433964.
The application discloses a UV photodetector and its preparation method, relating to the technical field of photodetectors. The UV photodetector comprises a first semiconductor layer, a second semiconductor layer, a quantum tunneling layer, a first electrode layer, and a second electrode layer. The first semiconductor layer comprises nickel oxide, while the second semiconductor layer comprises gallium oxide. A built-in electric field is formed on the side of the second semiconductor layer adjacent to the quantum tunneling layer, with the field directed from the second semiconductor layer toward the quantum tunneling layer.
By introducing a quantum tunneling layer between the first and second semiconductor layers and establishing a built-in electric field directed from the gallium oxide layer toward the quantum tunneling layer, the proposed approach improves the separation and collection efficiency of photogenerated carriers, reduces dark current, and enhances device responsivity and the photo-to-dark current ratio.
A Gallium Oxide Memristor and Preparation Method (Published September 25)
According to information released by the China National Intellectual Property Administration (CNIPA), Guangdong University of Technology has filed a patent application titled “A Gallium Oxide Memristor and Preparation Method.” The publication number is CN122825707A, and the application number is 2026110586939.
The invention discloses a gallium oxide memristor and its preparation method, relating to the technical field of semiconductor devices. The memristor comprises a bottom electrode, a resistive switching material layer formed on the bottom electrode, and a top electrode formed on the resistive switching material layer. The resistive switching material consists of cerium-doped gallium oxide and can be fabricated using a solution-based spin-coating method.
By doping gallium oxide with cerium to regulate defects in the material, the proposed approach improves the switching ratio and stability of the gallium oxide memristor.
A Method for Heteroepitaxial Growth of High-Quality Gallium Oxide Thin Films on Silicon/Silicon Carbide Substrates Using a Graphene Interlayer (Published September 25)
According to information released by the China National Intellectual Property Administration (CNIPA), Fudan University has filed a patent application titled “A Method for Heteroepitaxial Growth of High-Quality Gallium Oxide Thin Films on Silicon/Silicon Carbide Substrates Using a Graphene Interlayer.” The publication number is CN122825711A, and the application number is 2026109951791.
The invention relates to semiconductor materials, particularly a method for heteroepitaxial growth of high-quality gallium oxide thin films on silicon/silicon carbide substrates using a graphene interlayer.
The preparation method comprises the following steps: (1) pretreating the surfaces of silicon and silicon carbide substrates; (2) depositing a copper film on the pretreated substrate surfaces; (3) growing a continuous, defect-free two-dimensional graphene lattice barrier layer on the copper film by chemical vapor deposition (CVD); and (4) using the two-dimensional graphene lattice barrier layer as a growth platform to deposit a gallium oxide thin film by ultrasonic spray chemical vapor deposition.
The method enables the preparation of high-quality gallium oxide thin films while offering low raw-material costs, with gallium chloride, methane, and copper used as the primary materials. It also features compatibility with conventional equipment and fixed process parameters, making it suitable for industrial-scale implementation.
A Gallium Oxide Power Diode with a Spatially Modulated Junction-Termination Extension and Preparation Method (Published September 25)
According to information released by the China National Intellectual Property Administration (CNIPA), Chongqing University of Technology has filed a patent application titled “A Gallium Oxide Power Diode with a Spatially Modulated Junction-Termination Extension and Preparation Method.” The publication number is CN122825484A, and the application number is 202610929782X.
The invention discloses a gallium oxide power diode featuring a spatially modulated junction-termination extension (JTE) structure and its preparation method. The structure uses periodically arranged nickel oxide (NiO) rings to distribute the electric field more uniformly and alleviate electric-field crowding near the anode.
The device structure was simulated and optimized using technology computer-aided design (TCAD) software. The results show that the maximum breakdown voltage (VBR) of the double-layer structure reaches 6.05 kV. At a withstand voltage of 5 kV, the relative doping window (RDW) expands to ±80%, outperforming comparable β-Ga₂O₃ devices previously reported, which achieved 3 kV and ±50%.
In addition to its high-voltage capability, the device maintains a specific on-resistance(Ron,sp) of 3.55 mΩ·cm² and a power figure of merit (PFOM) of 10.31 GW/cm².
This design offers a viable approach to β-Ga₂O₃ power devices that combine high breakdown voltage with a wide process window, providing useful insights for improving device reliability and manufacturing feasibility.
A Method for Preparing Highly Conductive n-Type β-Ga₂O₃ Homoepitaxial Layers through Sn and Si Co-Doping (Published September 25)
According to information released by the China National Intellectual Property Administration (CNIPA), Xiamen Quanga Semiconductor Technology Co., Ltd. has filed a patent application titled “A Method for Preparing Highly Conductive n-Type Gallium Oxide Homoepitaxial Layers through Sn and Si Co-Doping.” The publication number is CN122811910A, and the application number is 2026109274387.
The invention discloses a method for preparing highly conductive n-type β-Ga₂O₃ homoepitaxial layers through Sn and Si co-doping. By co-doping with silicon and tin, the method exploits the complementary lattice-site occupancy of the two elements and their synergistic effects in regulating defect formation. This approach enables the controlled fabrication of high-performance β-Ga₂O₃ epitaxial layers with both high carrier concentrations and high carrier mobility while maintaining a high dopant activation rate.
The method addresses the limitations of single-element Si or Sn doping, including mobility degradation at high doping concentrations, increased defect density, and difficulties in doping regulation. It provides support for expanding the application of β-Ga₂O₃ epitaxial layers in key functional layers, such as ohmic contact layers in power devices and transparent electrodes in photodetectors.
A Multilayer Composite Insulating Passivation and Protection Structure for Gallium Oxide Surfaces (Published September 29)
According to information released by the China National Intellectual Property Administration (CNIPA), Beijing Orient Semi Co., Ltd. has filed a patent application titled “A Multilayer Composite Insulating Passivation and Protection Structure for Gallium Oxide Surfaces.” The publication number is CN122847242A, and the application number is 2026111298854.
The invention discloses a multilayer composite insulating passivation and protection structure for gallium oxide surfaces, relating to surface passivation and interface engineering for gallium oxide power devices. The structure is positioned at the high-field boundary region of an all-n-type β-Ga₂O₃ device and comprises three components: an interfacial nucleation repair region directly bonded to the β-Ga₂O₃ surface, a continuous primary insulating layer extending from the high-field region into the adjacent low-field region, and a localized field-redistribution overlayer covering only the high-field region.
The localized field-redistribution overlayer has a higher dielectric constant than the continuous primary insulating layer. Their spatial arrangement ensures that the high-dielectric-constant material does not directly contact the β-Ga₂O₃ surface.
The interfacial nucleation repair region establishes a low-defect nucleation starting point, while the continuous primary insulating layer isolates fixed charges in the outer layers. The localized field-redistribution overlayer shifts the electric-field peak at the electrode edge or field-plate termination outward.
The invention is applicable to vertical β-Ga₂O₃ Schottky barrier diodes and insulated-gate power devices.
A Silicon-Based Gallium Oxide Avalanche Photodetector, Preparation Method Thereof, and Fire Detection System (Published September 29)
According to information released by the China National Intellectual Property Administration (CNIPA), Hubei University has filed a patent application titled “A Silicon-Based Gallium Oxide Avalanche Photodetector, Preparation Method Thereof, and Fire Detection System.” The publication number is CN122846831A, and the application number is 2026109783052.
The invention discloses a silicon-based avalanche photodetector, its preparation method, and a fire detection system. The photodetector comprises an n-type silicon substrate with two layers sequentially formed on it. A buffer layer is used to mitigate lattice mismatch, while band engineering is employed to regulate the electric field and achieve avalanche multiplication, thereby improving deep-ultraviolet detection sensitivity.
The device is fabricated using metal-organic chemical vapor deposition (MOCVD) for epitaxial growth, together with conventional semiconductor micro- and nanofabrication processes, offering good process compatibility and scalability for mass production.
The fire detection system incorporating the photodetector features signal conditioning, multistage filtering, status determination, and wireless communication via MQTT, enabling real-time monitoring of flame conditions.
Designed for solar-blind ultraviolet detection, the invention is particularly suitable for early fire warning in industrial facilities, buildings, and similar environments.
A Substrate Processing Method for Improving the Crystal Quality of Gallium Oxide Heteroepitaxial Layers (Published September 29)
According to information released by the China National Intellectual Property Administration (CNIPA), Xiamen Quanga Semiconductor Technology Co., Ltd. has filed a patent application titled “A Substrate Processing Method for Improving the Crystal Quality of Gallium Oxide Heteroepitaxial Layers.” The publication number is CN122847047A, and the application number is 2026109275445.
The invention discloses a substrate processing method for improving the crystal quality of gallium oxide heteroepitaxial layers. After cleaning a sapphire substrate, the method first performs high-temperature annealing in a nitrogen atmosphere to repair the substrate surface, followed by surface passivation using argon plasma treatment. The processed substrate is then used for the growth of β-Ga₂O₃ by metal-organic chemical vapor deposition (MOCVD), producing high-quality β-Ga₂O₃ heteroepitaxial wafers.
Through a multilevel synergistic approach combining physical structure optimization, interface passivation, and epitaxial growth optimization, the invention addresses issues such as disordered domain orientations and high defect densities arising from symmetry mismatch. This method enables the fabrication of β-Ga₂O₃ heteroepitaxial layers with improved crystal quality.
