【Patenes】Gallium Oxide Patent Weekly Report (Issue 14, October)

      To further strengthen information exchange within the gallium oxide industry and help stakeholders stay informed of the latest technological developments, the Asian Gallium Oxide Alliance (AGOA) has launched the Gallium Oxide Patent Weekly column. This series will continuously compile and publish newly disclosed patent applications and technological advances in the gallium oxide field.

      As an important indicator of technological innovation, patents reflect R&D trends and strategic layout across the industrial chain. This column focuses on crystal growth, material preparation, defect engineering, device development, process optimization, and emerging applications, providing enterprises, universities, and research institutes with insights into technology trends while supporting the continued development of the gallium oxide industry.

      This fourteenth issue reviews gallium oxide-related patent applications published during the first and second weeks of October 2026 (October 1–October 11).

 

1.Growth Method for Gallium Oxide Epitaxy and Gallium Oxide Epitaxial Layer (Published October 2)

      According to information released by the China National Intellectual Property Administration, the 46th Research Institute of China Electronics Technology Group Corporation (CETC) has filed a patent application titled “Growth Method for Gallium Oxide Epitaxy and Gallium Oxide Epitaxial Layer.” The publication number is CN122856365A, and the application number is 2026112587014.

      The invention provides a method for growing gallium oxide epitaxy and a gallium oxide epitaxial layer, relating to the technical field of gallium oxide growth. The method comprises the following steps:

      When a first preset temperature is reached, oxygen is introduced into the chamber to remove subsurface damage from the gallium oxide substrate. Oxygen and chlorine gas are then introduced into the first and second pipelines, respectively, to grow a gallium oxide buffer layer on the substrate. The inlet of the second pipeline is connected to one end of a quartz tube containing metallic gallium.

      When the buffer-layer growth time reaches a first preset duration, the oxygen in the second pipeline is replaced with ozone at a first preset flow rate. Meanwhile, hydrogen is introduced at a second preset flow rate through the inlet of a third pipeline. This enables the growth of the gallium oxide epitaxial layer. The outlet of the third pipeline is connected to the outlet of the quartz tube, allowing gallium chloride and hydrogen to mix uniformly.

      The invention aims to achieve a balance between epitaxial quality and growth efficiency.

 

2.In-Situ High-Temperature Annealing Method for Gallium Oxide Homoepitaxial Wafers and Homoepitaxial Wafers (Published October 2)

      According to information released by the China National Intellectual Property Administration, the 46th Research Institute of China Electronics Technology Group Corporation (CETC) has filed a patent application titled “In-Situ High-Temperature Annealing Method for Gallium Oxide Homoepitaxial Wafers and Homoepitaxial Wafers.” The publication number is CN122856369A, and the application number is 2026111919173.

      The invention relates to the field of epitaxial wafer fabrication, particularly an in-situ high-temperature annealing method for gallium oxide homoepitaxial wafers and the resulting wafers.

      The method comprises the following steps:

      After the growth of a gallium oxide homoepitaxial wafer is completed in a hydride vapor phase epitaxy (HVPE) chamber, the chamber is evacuated and then filled with an inert gas to establish an oxygen-free inert atmosphere.

      The HVPE chamber is then heated to the annealing temperature, which must be higher than the growth temperature of the gallium oxide homoepitaxial wafer and no lower than 1,100°C.

      The wafer is held at the annealing temperature for a predetermined period to complete the in-situ annealing process. After the HVPE chamber has cooled down, the gallium oxide homoepitaxial wafer is removed.

      The invention is designed to ensure the recovery of resistivity in HVPE-grown gallium oxide homoepitaxial wafers while reducing energy consumption and processing time.

 

3.Method, Device, and Medium for Detecting Defects in Gallium Oxide Crystals Grown by the EFG Method (Published October 2)

      According to information released by the China National Intellectual Property Administration, Shandong SINOGa Valley Semiconductor Technology Co., Ltd. has filed a patent application titled “Method, Device, and Medium for Detecting Defects in Gallium Oxide Crystals Grown by the EFG Method.” The publication number is CN122866092A, and the application number is 2026110617956.

      The application discloses a method, device, and medium for detecting defects in gallium oxide crystals grown using the edge-defined film-fed growth (EFG) method, relating to the field of image processing.

      The method comprises the following steps:

      First, multi-field-of-view image sequences of the surface under inspection are acquired and fused to generate a panoramic image, which is then enhanced at multiple scales.

      Next, the enhanced image is segmented using a joint segmentation strategy comprising separate branches for macroscopic defect detection and microscopic dislocation detection, producing masks of candidate defect regions.

      Each candidate defect region is then classified and quantified to obtain its defect-type label and parameters, including defect area, equivalent diameter, and perimeter.

      Based on the defect-type labels and quantitative parameters, nearest-neighbor distances and radial distributions are calculated to derive spatial distribution characteristics, while the density of dislocation etch pits is also statistically evaluated.

      Finally, a predefined quality grading model is applied to comprehensively assess these parameters, determine the crystal quality grade, and generate an inspection report.

 

4.HVPE Epitaxial Uniformity Control and Defect Suppression Process (Published October 2)

      According to information released by the China National Intellectual Property Administration, Beijing Orient Semi Co., Ltd. has filed a patent application titled “HVPE Epitaxial Uniformity Control and Defect Suppression Process.” The publication number is CN122856359A, and the application number is 2026110423912.

      The invention discloses a process for controlling epitaxial uniformity and suppressing defects during hydride vapor phase epitaxy (HVPE), relating to the field of single-crystal growth.

      The process involves placing a gallium oxide substrate in an HVPE reaction chamber, evacuating the chamber and heating it, and introducing a halogen-containing gas to react with metallic gallium and generate gaseous gallium halides, which are then transported into the reaction chamber for epitaxial growth.

      A coordinated source-zone gas supply control strategy is employed to regulate gas flow rates and maintain the reactant concentration distribution, while coordinated substrate thermal-field control is used to adjust the temperature distribution.

      As epitaxial growth transitions from the nucleation stage to the drift-layer growth stage, a graded transition control strategy is applied to gradually adjust process parameters. Meanwhile, coordinated exhaust-flow-field control regulates the exhaust flow rate and pressure to remove reaction by-products. Through the combined action of these control strategies, a thick gallium oxide drift layer is grown continuously.

      The invention aims to improve gas transport and the growth environment within the reaction chamber, enhance thickness uniformity in thick drift layers, and reduce dislocation and defect densities.

 

5.Gallium Oxide-Based Optoelectronic Device and Manufacturing Method (Published October 2)

      According to information released by the China National Intellectual Property Administration, the University of Science and Technology of China (USTC) has filed a patent application titled “Gallium Oxide-Based Optoelectronic Device and Manufacturing Method.” The publication number is CN122871771A, and the application number is 2026110339236.

      The invention provides a gallium oxide-based optoelectronic device and a method for manufacturing the same, relating to the technical field of optoelectronic detection and storage.

      The manufacturing method comprises the following steps:

      A light-absorbing layer comprising a gallium oxide thin film is formed on a substrate. An anode and a cathode are then formed separately on the light-absorbing layer to create a metal–semiconductor–metal (MSM) structure.

      The anode and cathode each comprise an adhesion layer and a metal layer deposited on top of the adhesion layer. The adhesion layer comprises an oxidizable metal.

      The MSM structure is then subjected to thermal annealing in an inert atmosphere to obtain the gallium oxide-based optoelectronic device.

      The invention enables passive optical information storage using the gallium oxide-based optoelectronic device.

 

6.Gallium Oxide Liquid-Phase Epitaxy Furnace with Electromagnetic Stirring and Process Control Functions (Published October 2)

      According to information released by the China National Intellectual Property Administration, Hubei University has filed a patent application titled “Gallium Oxide Liquid-Phase Epitaxy Furnace with Electromagnetic Stirring and Process Control Functions.” The publication number is CN122856339A, and the application number is 2026108935202.

      The invention relates to crystal growth equipment and discloses a gallium oxide liquid-phase epitaxy furnace featuring electromagnetic stirring and process control. The furnace comprises a furnace body, a crucible-supporting and thermal-insulation base, a pulling and rotation mechanism, a lifting mechanism, a magnetic field system, a mounting platform, and a proportional–integral–derivative (PID) controller.

      The magnetic field system comprises an outer housing, a coil frame, racetrack-shaped excitation coils, electrical leads for the coils, a variable-frequency magnetic field control unit, and a first support frame.

      The coil frame is arranged around and fixed within a first annular cavity inside the outer housing. The racetrack-shaped excitation coils are embedded in their corresponding coil-support blocks.

      By adjusting the amplitude and frequency of the excitation current, the variable-frequency magnetic field control unit supplies alternating current to the coils to generate a horizontally rotating magnetic field within the crucible. Alternatively, it adjusts the excitation current amplitude and supplies direct current to generate a horizontal static magnetic field.

      The invention enables uniform mixing throughout the melt while effectively suppressing unsteady fluid flow, thereby significantly improving the quality of gallium oxide epitaxial growth.

 

7.Directional Solidification Apparatus and Method for β-Gallium Oxide Single-Crystal Growth (Published October 9)

      According to information released by the China National Intellectual Property Administration, Beijing MIG Semiconductor Co., Ltd.‌ has filed a patent application titled “Directional Solidification Apparatus and Method for β-Gallium Oxide Single-Crystal Growth.” The publication number is CN122879810A, and the application number is 202611364658X.

      The invention discloses an apparatus and method for growing β-gallium oxide single crystals by directional solidification.

      The apparatus comprises a furnace body containing three vertically arranged chambers: a melting chamber at the top, a crystal-heating chamber beneath it that communicates with the melting chamber through a first opening, and a crystal growth and annealing chamber below the crystal-heating chamber that communicates with it through a second opening.

      A feed tube passes through an opening at the top of the melting chamber. A feed funnel is positioned inside the chamber, with its upper receiving port facing the lower outlet of the feed tube. A vertically extending guide rod is provided along the edge of the liquid-dripping hole at the bottom of the funnel. The guide rod passes through both the first and second openings.

      A support tray is positioned inside the crystal growth and annealing chamber, with its seed-crystal mounting position vertically aligned with the guide rod. A support rod passes through an opening at the bottom of the chamber and supports the tray while allowing vertical movement and rotation about the vertical axis.

      In this invention, the top of the gallium oxide seed crystal is partially melted to support the melt. The melt is then joined to the seed crystal and shaped through its own surface tension. The process eliminates the need for an iridium crucible, thereby avoiding contamination caused by the dissolution of iridium into the material.

 

8.Apparatus and Method for β-Gallium Oxide Single-Crystal Growth by the Casting Method (Published October 9)

      According to information released by the China National Intellectual Property Administration, Beijing MIG Semiconductor Co., Ltd.‌ has filed a patent application titled “Apparatus and Method for β-Gallium Oxide Single-Crystal Growth by the Casting Method.” The publication number is CN122879809A, and the application number is 2026113031142.

      The invention discloses an apparatus and method for growing β-gallium oxide single crystals using a casting method.

      In the apparatus, a mounting flange is provided around the outer perimeter of the upper opening of a feed cylinder, allowing it to engage with the outer perimeter of the opening at the top of the furnace body. A feed tube passes through an opening in the upper portion of the thermal insulation structure. Its upper end is connected to the lower outlet of the feed cylinder, while its lower end connects to the feed inlet in the crucible lid.

      A material reservoir cylinder is positioned inside the feed cylinder. A cover plate closes the upper opening of the reservoir cylinder and engages with the outer perimeter of the feed cylinder’s upper opening.

      A screen is installed inside the material reservoir cylinder and can reciprocate along its central axis. It forms a sliding seal with the cylinder’s inner wall. A vibration mechanism drives the screen’s reciprocating motion. A load cell is positioned between the cover plate and the outer perimeter of the feed cylinder’s upper opening.

      A reservoir cover is positioned above the furnace body and encloses the opening at the top of the furnace.

      The invention is designed to enable the growth of large-sized, low-defect β-gallium oxide single crystals.

 

9.Czochralski Liquid-Phase Epitaxy Method for Gallium Oxide Crystal Growth and Applications Thereof (Published October 9)

      According to information released by the China National Intellectual Property Administration, Hangzhou Garen Semiconductor Co., Ltd. has filed a patent application titled “Czochralski Liquid-Phase Epitaxy Method for Gallium Oxide Crystal Growth and Applications Thereof.” The publication number is CN122879815A, and the application number is 2026112506549.

      The invention relates to gallium oxide crystal technology and, more specifically, to a Czochralski liquid-phase epitaxy method for gallium oxide crystal growth and its applications.

      A large-sized gallium oxide seed crystal with a maximum inscribed circle diameter of at least 2 inches in cross-section is provided and fixed to the lower end of a seed holder. The seed crystal is then lowered until its bottom surface contacts the gallium oxide melt, initiating Czochralski liquid-phase epitaxial growth. Upon completion of growth, the resulting gallium oxide crystal is separated from the melt.

      By employing a large-sized gallium oxide seed crystal, the invention eliminates the need for a shoulder-expansion stage during Czochralski liquid-phase epitaxial growth. The seed crystal is approximately the same size as the target crystal, eliminating the need for diameter-expansion growth and thereby avoiding shoulder-related defects caused by crystallographic anisotropy. The patent states that this approach reduces the shoulder-defect rate to zero.

      The approach also optimizes the stress distribution within the crystal. The large-sized seed crystal forms a fully covered, large-area single-crystal interface with the epitaxial crystal, helping distribute the mechanical stress caused by the crystal's own weight and address cracking and detachment along cleavage planes.

      The invention aims to achieve both large crystal dimensions and high crystal quality in gallium oxide growth.

 

10.Heteroepitaxial Growth Method for Gallium Oxide Thin Films on Silicon Substrates (Published October 9)

      According to information released by the China National Intellectual Property Administration, Nanjing University of Posts and Telecommunications has filed a patent application titled “Heteroepitaxial Growth Method for Gallium Oxide Thin Films on Silicon Substrates.” The publication number is CN122892460A, and the application number is 2026110983596.

      The invention discloses a method for heteroepitaxial growth of gallium oxide thin films on silicon substrates, relating to the field of semiconductor materials.

      In this method, the fluidity of liquid gallium is utilized to form an ultrathin, two-dimensional gallium oxide seed layer on a silicon substrate through weak-bond coupling. This seed layer then serves as a lattice-matching template for the heteroepitaxial growth of gallium oxide thin films with a preferred β-phase (−201) orientation, using plasma-enhanced chemical vapor deposition (PECVD).

      The two-dimensional gallium oxide seed layer serves a dual purpose on the silicon substrate: it acts as both a lattice-matching template and an interfacial buffer layer. This approach enables the growth of high-quality gallium oxide thin films with a preferred (−201) orientation on silicon substrates, which previously could not readily support such preferential epitaxial growth.

      The invention features a simple, low-cost process and provides a high-quality thin-film fabrication approach for high-performance gallium oxide power devices, ultraviolet photodetectors, and other applications.

 

11.Deep Trench Etching and Sidewall Passivation Process for Gallium Oxide (Published October 9)

      According to information released by the China National Intellectual Property Administration, Beijing Orient Semi Co., Ltd. has filed a patent application titled “Deep Trench Etching and Sidewall Passivation Process for Gallium Oxide.” The publication number is CN122892472A, and the application number is 2026110657629.

      The invention discloses a process for deep trench etching and sidewall passivation of gallium oxide, falling within the technical field of semiconductor device manufacturing. The process involves forming a trench etching window on the surface of a gallium oxide single-crystal epitaxial wafer, followed by multistage etching of the exposed gallium oxide using inductively coupled plasma reactive ion etching (ICP-RIE) to form a deep trench structure. Acid treatment combined with oxygen annealing is then used to regulate etching-induced defects. Subsequently, alkaline wet etching is performed to round the corners at the top and bottom of the trench. Finally, an aluminum oxide interfacial passivation layer and a silicon dioxide or silicon nitride (SiNₓ) bulk passivation layer are deposited sequentially to form a composite passivation structure.

      Through the synergistic effects of etch damage control, defect regulation, trench profile optimization, and interfacial passivation, the invention reduces sidewall defects and localized electric field concentration in gallium oxide deep trenches. This improves the reverse breakdown performance of trench Schottky barrier diodes and reduces leakage current, making the process suitable for manufacturing high-voltage gallium oxide power semiconductor devices.

 

12.Method, Device, and Medium for Monitoring Gallium Oxide Crystal Growth Based on the Edge-Defined Film-Fed Growth (EFG) Method (Published October 9)

      According to information released by the China National Intellectual Property Administration, Shandong SINOGa Valley Semiconductor Technology Co., Ltd. has filed a patent application titled “Method, Device, and Medium for Monitoring Gallium Oxide Crystal Growth Based on the Edge-Defined Film-Fed Growth (EFG) Method.” The publication number is CN122887837A, and the application number is 2026110617937.

      This application discloses a method, device, and medium for monitoring gallium oxide crystal growth based on the EFG method, relating to image processing technology. The method involves preprocessing growth images to obtain images with enhanced interface features, followed by dynamic extraction of the solid–liquid growth interface region from the enhanced images. The mean grayscale value of this region is then calculated and compared with a preset grayscale threshold to determine a first temperature state of the solid–liquid interface region. Based on this temperature state, the pixel-based crystal width and the fitting dispersion of the solid–liquid interface edge are calculated to determine a second temperature state. The heating power of the crystal growth furnace is dynamically adjusted according to the second temperature state until the gallium oxide crystal growth cycle is complete.

      This method addresses a technical problem in existing gallium oxide crystal growth monitoring technologies: the inability to provide generalized monitoring across different degrees of overheating and underheating.

 

13.Gallium Oxide Layer and Preparation Method Thereof (Published October 9)

      According to information released by the China National Intellectual Property Administration, Mozi Laboratory has filed a patent application titled “Gallium Oxide Layer and Preparation Method Thereof.” The publication number is CN122879821A, and the application number is 2026110190240.

      The invention relates to the field of semiconductor materials and discloses a gallium oxide layer and a method for preparing the same. In this method, a GaN epitaxial wafer is used as the substrate. After cleaning, gallium (Ga) is deposited onto the GaN substrate surface. Taking advantage of the etching effect of Ga on GaN at a specific temperature, a GaN film with a porous structure is formed. Residual Ga is then removed by soaking the film in a solution, after which the porous GaN film undergoes high-temperature oxidation in an oxygen-rich atmosphere to obtain a porous gallium oxide film.

      The porous structure functions similarly to a patterned substrate surface. Furthermore, homoepitaxial growth of gallium oxide avoids interference from factors such as lattice mismatch and differences in thermal expansion. Consequently, homoepitaxial growth of a gallium oxide layer on the porous gallium oxide film can effectively release stress and reduce dislocations, ultimately yielding a high-quality gallium oxide layer.

      The proposed preparation method is relatively low-cost and enables the fabrication of high-quality, large-area gallium oxide layers, potentially enhancing the practical application of gallium oxide.

 

14.An Ultra-High-Voltage Gallium Oxide Insulated-Gate Heterojunction Bipolar Power Device and Method for Fabricating the Same (Published October 9)

      According to information released by the China National Intellectual Property Administration, University of Electronic Science and Technology of China has filed a patent application titled “An Ultra-High-Voltage Gallium Oxide Insulated-Gate Heterojunction Bipolar Power Device and Method for Fabricating the Same.” The publication number is CN122892199A, and the application number is 2026110186940.

      The invention relates to semiconductor technology and specifically provides an ultra-high-voltage gallium oxide insulated-gate heterojunction bipolar power device and a method for fabricating the same. Each device cell comprises a substrate layer, a buffer layer, a drift region, a heavily doped P-type collector region, a collector electrode, a passivation layer, a lightly doped P-type region, a gate electrode, an emitter electrode, a heavily doped P-type emitter region, a gate dielectric layer, heavily doped N-type gallium oxide, and a current-blocking layer.

      The current-blocking layer enables normally-off, enhancement-mode operation, ensuring safe and reliable device performance. Holes injected from the heavily doped P-type collector region into the drift region produce a conductivity modulation effect, substantially reducing the on-state voltage drop and increasing current density. In addition, the lightly doped P-type region, gate dielectric layer, and drift region form a superjunction-like structure. By introducing a vertical electric-field component, this structure optimizes the electric-field distribution in the drift region, achieving an excellent trade-off between breakdown voltage and specific on-resistance.

      The device is suitable for ultra-high-voltage power conversion applications.

 

15.Gallium Oxide Transistor Device (Published October 9)

      According to information released by the China National Intellectual Property Administration, Ningbo Yongjiang Laboratory has filed a patent application titled “Gallium Oxide Transistor Device.” The publication number is CN122892217A, and the application number is 2026108045802.

      This application discloses a gallium oxide transistor device comprising a substrate layer, a β-Ga₂O₃ buffer layer stacked on the substrate surface and grown with ozone assistance, and a channel layer stacked on the surface of the β-Ga₂O₃ buffer layer facing away from the substrate.

      By inserting an ozone-assisted-grown β-Ga₂O₃ buffer layer between the substrate and the channel layer to replace the conventional unintentionally doped buffer layer, the proposed device effectively suppresses off-state leakage at high temperatures, thereby improving high-temperature reliability.

      The ozone-assisted-grown β-Ga₂O₃ buffer layer contains a high concentration of gallium vacancies and gallium–oxygen vacancy pairs. These defects act as deep acceptor levels that are deeper than Fe-related acceptor levels, enabling more effective electron trapping at elevated temperatures. This helps suppress high-temperature leakage paths and significantly reduce the off-state leakage current. The structure also optimizes the current path, further improving the device’s high-temperature stability and overall power consumption performance.

 

16.Gallium Oxide JBS Diode Based on Ion-Implantation-Induced Reduction and Method for Fabricating the Same (Published October 9)

      According to information released by the China National Intellectual Property Administration, the 13th Research Institute of China Electronics Technology Group Corporation (CETC) has filed a patent application titled “Gallium Oxide JBS Diode Based on Ion-Implantation-Induced Reduction and Method for Fabricating the Same.” The publication number is CN122892195A, and the application number is 2025111430726.

      The invention relates to gallium oxide device technology and provides a gallium oxide junction barrier Schottky (JBS) diode based on ion-implantation-induced reduction, together with a method for fabricating the same.

      The method involves epitaxially growing a lightly doped n-type layer on the upper surface of a heavily doped n-type gallium oxide substrate. P-type ions are then implanted into multiple isolated regions on the upper surface of the n-type epitaxial layer to form implantation regions. High-temperature thermal annealing is subsequently performed on these regions in a reducing atmosphere to activate the implanted p-type ions, thereby forming p-type ion-implanted regions. A cathode electrode is fabricated on the lower surface of the heavily doped n-type gallium oxide substrate, and an anode electrode is fabricated on its upper surface to complete the gallium oxide JBS diode.

      By combining ion implantation with a reducing gas atmosphere, the invention reduces the difficulty of fabricating p-type-doped gallium oxide and simplifies the manufacturing process for gallium oxide JBS diodes.

      In addition to patents focusing on gallium oxide materials, several patents published this week also involve the application of gallium oxide as a functional material in other fields, which are provided for readers’ reference.

 

1.Method for Stepwise Extraction of Gallium from an Indium–Gallium Mixed Solution and Preparation of Gallium Oxide (Published October 2)

      According to information released by the China National Intellectual Property Administration, Rong'an Ruizhi Environmental Protection Technology Co., Ltd. has filed a patent application titled “Method for Stepwise Extraction of Gallium from an Indium–Gallium Mixed Solution and Preparation of Gallium Oxide.” The publication number is CN122855905A, and the application number is 2026111394885.

      The invention discloses a method for stepwise extraction of gallium from an indium–gallium mixed solution and preparation of gallium oxide, relating to hydrometallurgy of non-ferrous metals and the extraction of rare and dispersed metals. The method comprises the following steps:

      An indium–gallium mixed solution is provided in the form of an acidic aqueous solution containing indium ions and gallium ions. A first extraction system is then used to extract indium ions selectively into the organic phase, while gallium ions remain in the aqueous phase, yielding an indium-enriched organic phase and a gallium-containing raffinate. The first extraction system comprises an acidic phosphorus-based extractant and a first diluent.

      Through a carefully designed stepwise extraction process, the invention achieves efficient and selective separation of indium and gallium. First, an acidic phosphorus-based extractant is used under specific conditions to selectively extract indium into the organic phase while leaving gallium in the aqueous phase, thereby achieving preliminary separation of the two metals. The pH of the gallium-containing raffinate is then adjusted, after which an oxime-based or amine-based extractant is used to selectively extract gallium.