Patents
【Patenes】Gallium Oxide Patent Weekly Report (Issue 26, October)
日期：2026-11-06阅读：19
To further strengthen information exchange within the gallium oxide industry and help stakeholders stay informed of the latest technological developments, the Asian Gallium Oxide Alliance (AGOA) has launched the Gallium Oxide Patent Weekly column. This series will continuously compile and publish newly disclosed patent applications and technological advances in the gallium oxide field.
As an important indicator of technological innovation, patents reflect R&D trends and strategic layout across the industrial chain. This column focuses on crystal growth, material preparation, defect engineering, device development, process optimization, and emerging applications, providing enterprises, universities, and research institutes with insights into technology trends while supporting the continued development of the gallium oxide industry.
This seventeenth issue reviews gallium oxide-related patent applications published during the fourth weeks of October 2026 (October 26–November 25).
Gallium Oxide PIN Diode Based on Ion-Implantation-Induced Reduction and Preparation Method (Published on October 27)
According to information released by the China National Intellectual Property Administration (CNIPA), the 13th Research Institute of China Electronics Technology Group Corporation (CETC) has filed a patent application titled "Gallium Oxide PIN Diode Based on Ion-Implantation-Induced Reduction and Preparation Method." The publication number is CN122995168A, and the application number is 2025111430622.
The invention provides a gallium oxide PIN diode based on ion-implantation-induced reduction and a method for its preparation, relating to the technical field of gallium oxide devices. The method uses a heavily doped n-type gallium oxide substrate as the N layer, followed by the formation of an I layer on the substrate. P-type ions are then implanted into the I layer, and high-temperature annealing in a reducing gas atmosphere is performed to activate the implanted ions and achieve p-type doping, thereby forming the P layer.
Through a reduction reaction, the reducing gas removes oxygen atoms from the gallium oxide lattice, allowing the implanted p-type ions to occupy oxygen lattice sites and capture electrons from gallium atoms, thereby generating holes and achieving p-type ion-implantation doping. This approach reduces the difficulty of preparing p-type-doped gallium oxide. Cathode and anode electrodes are subsequently fabricated to complete the PIN diode structure, simplifying the overall fabrication process of gallium oxide PIN diodes.
Full-Spectrum Natural-Light Chip Based on Group VIA Element-Doped Amorphous Gallium Oxide and Preparation Method (Published on October 27)
According to information released by the China National Intellectual Property Administration (CNIPA), Mozi Laboratory has filed a patent application titled "Full-Spectrum Natural-Light Chip Based on Group VIA Element-Doped Amorphous Gallium Oxide and Preparation Method." The publication number is CN122995363A, and the application number is 2026111142916.
The invention provides a full-spectrum natural-light chip based on Group VIA element-doped amorphous gallium oxide and a method for its preparation. The chip comprises a p-type semiconductor layer, an n-type semiconductor layer, and an amorphous light-emitting layer positioned between the p-type and n-type semiconductor layers. The amorphous light-emitting layer is made of amorphous gallium oxide doped with Group VIA elements, including at least one of sulfur (S), selenium (Se), and tellurium (Te). These elements substitute for oxygen sites in the amorphous gallium oxide, introducing anion doping to reduce its bandgap.
The invention enables a single semiconductor chip to directly emit continuous, full-spectrum natural light.
Method for Growing Gallium Oxide Epitaxy by High-Pressure Liquid-Phase Epitaxy, Epitaxial Wafer, and Electronic Device (Published on October 27)
According to information released by the China National Intellectual Property Administration (CNIPA), Hangzhou Garen Semiconductor Co., Ltd. has filed a patent application titled "Method for Growing Gallium Oxide Epitaxy by High-Pressure Liquid-Phase Epitaxy, Epitaxial Wafer, and Electronic Device." The publication number is CN122980017A, and the application number is 2026112008933.
The invention relates to the technical field of epitaxial wafers, and specifically concerns a method for growing gallium oxide epitaxy by high-pressure liquid-phase epitaxy, as well as an epitaxial wafer and an electronic device.
The method for growing a gallium oxide epitaxial layer by high-pressure liquid-phase epitaxy comprises the following steps: first, heating a crucible containing at least metallic gallium under an inert atmosphere to obtain a liquid gallium melt; then, bringing a substrate into contact with the gallium melt under a high-pressure oxygen-containing atmosphere to grow either a p-type or an n-type epitaxial layer by liquid-phase epitaxy, thereby forming a gallium oxide epitaxial layer.
For the growth of a p-type epitaxial layer, the high-pressure oxygen-containing atmosphere also contains a nitrogen-containing gas. For the growth of an n-type epitaxial layer, metallic tin is additionally introduced into the crucible.
This method enables flexible switching between n-type and p-type conductivity in gallium oxide epitaxial layers on the same platform. It also balances crystal quality and growth efficiency while significantly reducing the density of crystallographic defects, such as dislocations and stacking faults.
Preparation Method and Application of Doped Gallium Oxide Powder (Published on October 27)
According to information released by the China National Intellectual Property Administration (CNIPA), Hangzhou Garen Semiconductor Co., Ltd. has filed a patent application titled "Preparation Method and Application of Doped Gallium Oxide Powder." The publication number is CN122980039A, and the application number is 2026114249046.
The invention relates to the field of semiconductor material preparation technology, and specifically concerns a method for preparing doped gallium oxide powder and its applications.
The preparation method comprises the following steps: (a) subjecting solid gallium chloride to a first sintering treatment; and (b) subjecting the product obtained after the first sintering treatment to a first pulsed gaseous doping treatment, a second pulsed gaseous doping treatment, oxidation, diffusion homogenization, and cooling.
During the solid-state sintering stage of gallium oxide, the method introduces dopant elements in the form of gaseous dopant sources through multiple pulsed injections. This approach enables in-situ doping as the gallium oxide lattice forms.
Semiconductor Device and Power Conversion Device (Published on October 30)
According to information released by the China National Intellectual Property Administration (CNIPA), Mitsubishi Electric Corporation has filed a patent application titled "Semiconductor Device and Power Conversion Device." The publication number is CN123023455A, and the application number is 2024800896529.
The semiconductor device comprises a gallium oxide semiconductor layer; an impurity layer formed within the surface region of a first main surface of the gallium oxide semiconductor layer, containing a first acceptor-type impurity, at least a portion of which is activated; a first recess formed by removing portions of the impurity layer and the gallium oxide semiconductor layer, with a depth shallower than that of the impurity layer; a first main electrode disposed above the first main surface; and a second main electrode disposed above a second main surface of the gallium oxide semiconductor layer.
Gallium Oxide Solar-Blind Ultraviolet Photodetector Based on a Microcavity Structure and Preparation Method (Published on October 30)
According to information released by the China National Intellectual Property Administration (CNIPA), Mozi Laboratory has filed a patent application titled "Gallium Oxide Solar-Blind Ultraviolet Photodetector Based on a Microcavity Structure and Preparation Method." The publication number is CN123021786A, and the application number is 2025105505246.
The invention discloses a gallium oxide solar-blind ultraviolet photodetector based on a microcavity structure and a method for its preparation. The fabrication process comprises the following steps: (1) depositing a highly reflective metal layer on a substrate; (2) depositing a gallium oxide layer on the highly reflective metal layer, followed by annealing; (3) depositing a semitransparent metal layer on the gallium oxide layer; and (4) depositing first and second contact electrodes, followed by annealing to complete device fabrication.
The invention enhances the absorption of target ultraviolet light within a relatively thin gallium oxide film through the microcavity structure, thereby improving photodetection performance. It also takes advantage of the optical properties of conductive metal films: they exhibit high reflectivity at greater thicknesses, while becoming semitransparent and retaining a certain degree of reflectivity when made thinner. By using the upper and lower metal layers simultaneously as reflectors in the microcavity structure and as the top and bottom conductive electrodes, the invention simplifies the device architecture.
The proposed design and fabrication approach features a simple process and low cost, making it suitable for potential large-scale commercial applications.
Cavity-Type Bulk Acoustic Wave Resonator and Preparation Method (Published on October 30)
According to information released by the China National Intellectual Property Administration (CNIPA), Fujian Sunwise Semiconductor Technology Co., Ltd. has filed a patent application titled "Cavity-Type Bulk Acoustic Wave Resonator and Preparation Method." The publication number is CN123019657A, and the application number is 2026108139814.
The invention relates to the technical field of resonator design and discloses a cavity-type bulk acoustic wave (BAW) resonator and a method for its preparation. The resonator comprises a first substrate, a support layer, a bottom electrode layer, a piezoelectric layer, a top electrode layer, and an acoustic reflection structure layer. The support layer has a cavity recessed into its upper surface. The acoustic reflection structure layer comprises a lower acoustic reflection structure and an upper acoustic reflection structure, both of which are closed structures. The bottom electrode layer fills the interior of the lower acoustic reflection structure and covers its surface, while the top electrode layer fills the interior of the upper acoustic reflection structure and covers its surface.
The invention effectively suppresses energy dissipation from the edges of the resonant region during the resonance process in resonators and filters, thereby further improving the quality factor (Q factor) of resonators using epitaxial materials such as gallium oxide as piezoelectric films.
Multifunctional Large-Area Ultra-Flat Amorphous Gallium Oxide Thin Film, Preparation Method, and Applications (Published on October 30)
According to information released by the China National Intellectual Property Administration (CNIPA), Shandong University has filed a patent application titled “Multifunctional Large-Area Ultra-Flat Amorphous Gallium Oxide Thin Film, Preparation Method, and Applications.” The publication number is CN123022128A, and the application number is 2026110367325.
The invention provides a multifunctional large-area ultra-flat amorphous gallium oxide thin film, along with its preparation method and applications. The preparation method involves using a gallium source, an oxygen source, and a surface-modifying agent as raw materials, and employing low-pressure chemical vapor deposition (LPCVD) to grow the multifunctional large-area ultra-flat amorphous gallium oxide thin film on a substrate with the assistance of the surface-modifying agent.
By introducing the surface-modifying agent during the LPCVD process, the method regulates the initial nucleation behavior, surface diffusion, lateral atomic relaxation, and interfacial adhesion of the Ga₂O₃ thin film. This promotes the transition of amorphous Ga₂O₃ growth from island-like aggregation to continuous lateral film growth, enabling the low-cost, large-area, and high-efficiency fabrication of amorphous Ga₂O₃ thin films that are ultra-smooth, continuous, uniform, and highly compatible with substrates. These films are suitable for flexible, transparent, omnidirectional, and self-powered solar-blind photodetectors.
Gallium Oxide Field-Effect Transistor with a Silicon Carbide Channel and Preparation Method (Published on October 30)
According to information released by the China National Intellectual Property Administration (CNIPA), Xidian University has filed a patent application titled “Gallium Oxide Field-Effect Transistor with a Silicon Carbide Channel and Preparation Method.” The publication number is CN123021727A, and the application number is 2026110690059.
The invention relates to the field of microelectronics and specifically proposes a gallium oxide field-effect transistor with a silicon carbide channel and its preparation method. The transistor comprises a SiC substrate layer, a p-type SiC epitaxial layer, an n-type Ga₂O₃ epitaxial layer, a gate trench, a source trench, an Al₂O₃ gate dielectric layer, a gate electrode, a source electrode, and a drain electrode.
The gate and source trenches extend into the p-type SiC layer, enabling normally-off operation with a positive threshold voltage and low on-resistance. The drain region is designed within the n-type Ga₂O₃ epitaxial layer, allowing the Ga₂O₃ material, which can withstand high electric fields, to operate under high electric-field conditions and effectively improve the breakdown voltage. The high thermal conductivity of the SiC substrate helps suppress self-heating effects, while the trench-gate structure enhances gate control over the channel and suppresses short-channel effects.
These design features enable Ga₂O₃ power devices to achieve high breakdown voltage, low on-resistance, a high figure of merit (FOM), and excellent thermal dissipation performance while operating in the normally-off mode.
Indium-Nitrogen Co-Doped Gallium Oxide Thin Film and Preparation Method (Published on October 30)
According to information released by the China National Intellectual Property Administration (CNIPA), Longteng Semiconductor Co., Ltd. has filed a patent application titled “Indium-Nitrogen Co-Doped Gallium Oxide Thin Film and Preparation Method.” The publication number is CN123005493A, and the application number is 202611147336X.
The invention discloses an indium-nitrogen co-doped gallium oxide thin film and its preparation method. The method comprises the following steps: selecting a carrier substrate and pretreating it; dissolving a gallium source, an indium source, and an in-situ reactive nitrogen source in a polar solvent containing a complexing stabilizer, followed by complexation at a constant temperature and aging to obtain an indium-nitrogen co-doped gallium oxide precursor sol; coating the pretreated carrier substrate with the precursor sol and drying it to form an amorphous thin film; and subjecting the amorphous thin film to two-stage annealing activation in an inert protective atmosphere to obtain the indium-nitrogen co-doped gallium oxide thin film.
The gallium oxide thin film prepared using this synergistic indium-nitrogen co-doping strategy takes advantage of the lattice expansion caused by the substitution of gallium cation sites with indium ions of a larger ionic radius. This compensates for the local lattice tensile stress induced when nitrogen anions substitute for oxygen sites, fundamentally overcoming the thermodynamic solid-solubility limit of nitrogen in gallium oxide.
In addition to patents focusing on gallium oxide materials, several patents published this week also involve the application of gallium oxide as a functional material in other fields, which are provided for readers’ reference.
Metal Oxide Semiconductor Heating Material, Preparation Method, Semiconductor Heating Element, and Sludge and Solid Waste Dewatering, Drying, and Volume Reduction System and Method (Published on October 30)
According to information released by the China National Intellectual Property Administration (CNIPA), Beijing University of Chemical Technology has filed a patent application titled “Metal Oxide Semiconductor Heating Material, Preparation Method, Semiconductor Heating Element, and Sludge and Solid Waste Dewatering, Drying, and Volume Reduction System and Method.” The publication number is CN123003274A, and the application number is 2026114022460.
The invention falls within the technical field of advanced dewatering and volume reduction of sludge and solid waste. Specifically, it relates to a metal oxide semiconductor heating material and its preparation, a semiconductor heating element, as well as a system and method for sludge and solid waste dewatering, drying, and volume reduction.
The metal oxide semiconductor heating material provided by the invention comprises 75–85% main-phase semiconductor powder, 5–12% ionic doping modifier, 3–8% low-temperature sintering aid, and 2–5% inorganic binding carrier. The main-phase semiconductor powder comprises titanium dioxide, zinc oxide, and gallium oxide, while the ionic doping modifier comprises antimony trioxide, manganese dioxide, and yttrium oxide.
The semiconductor heating element fabricated from this metal oxide semiconductor heating material features high electrothermal conversion efficiency, stable low-temperature self-limiting temperature control, resistance to acid and alkali corrosion, and minimal long-term power degradation. It is suitable for low-temperature, enclosed drying and volume-reduction treatment of various high-moisture-content sludges, including biological sludge from municipal wastewater treatment plants, chemical sludge, printing and dyeing sludge, and electroplating sludge.
